[3/8] drm/amd/amdgpu: Added a dwc quirk for Stoney platform

Commit Message

Alex Deucher June 23, 2017, 4:35 p.m. UTC

From: Vijendar Mukunda <[e-mail]>

Added DW_I2S_QUIRK_16BIT_IDX_OVERRIDE quirk for Stoney.

Supported format and bus width for I2S controller read
from I2S Component Parameter registers.
These are ready only registers.

For Stoney, I2S Component Parameter registers are programmed
to support 32 bit format and 4 bytes bus width only.

By setting this quirk, it will override 32 bit format with
16 bit format and 2 bytes as bus width for Stoney.

Reviewed-by: Alex Deucher <[e-mail]>
Signed-off-by: Vijendar Mukunda <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

Comments

Mark Brown June 28, 2017, 6:02 p.m. UTC | #1

On Fri, Jun 23, 2017 at 12:35:01PM -0400, Alex Deucher wrote:

> +	if (adev->asic_type == CHIP_STONEY) {
> +		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
> +			DW_I2S_QUIRK_COMP_PARAM1 |
> +			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
> +	} else {
> +		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
> +			DW_I2S_QUIRK_COMP_PARAM1;
> +	}

Quirks like this are better written as switch statements since that
makes it easier to handle further variants in future.

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 7a2a765..86b68f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -321,14 +321,25 @@  static int acp_hw_init(void *handle)
 		return -ENOMEM;
 	}
 
-	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+	if (adev->asic_type == CHIP_STONEY) {
+		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+	} else {
+		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+	}
 	i2s_pdata[0].cap = DWC_I2S_PLAY;
 	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
 	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
 	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
+	if (adev->asic_type == CHIP_STONEY) {
+		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			DW_I2S_QUIRK_COMP_PARAM1 |
+			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+	} else {
+		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			DW_I2S_QUIRK_COMP_PARAM1;
+	}
 
-	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-				DW_I2S_QUIRK_COMP_PARAM1;
 	i2s_pdata[1].cap = DWC_I2S_RECORD;
 	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
 	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;