From patchwork Thu Jun 29 21:34:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivi, Rodrigo" X-Patchwork-Id: 9817979 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3EFAF603D7 for ; Thu, 29 Jun 2017 21:34:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F27E28484 for ; Thu, 29 Jun 2017 21:34:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2310528504; Thu, 29 Jun 2017 21:34:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B610628421 for ; Thu, 29 Jun 2017 21:34:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1C1F6E728; Thu, 29 Jun 2017 21:34:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C6A96E719; Thu, 29 Jun 2017 21:34:21 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 29 Jun 2017 14:34:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,283,1496127600"; d="scan'208";a="102903938" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.72]) by orsmga004.jf.intel.com with ESMTP; 29 Jun 2017 14:34:17 -0700 From: Rodrigo Vivi To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus. Date: Thu, 29 Jun 2017 14:34:16 -0700 Message-Id: <1498772058-902-2-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498772058-902-1-git-send-email-rodrigo.vivi@intel.com> References: <1498772058-902-1-git-send-email-rodrigo.vivi@intel.com> Cc: mesa-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Anusha Srivatsa , Rodrigo Vivi X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa Cc: Clinton Taylor Signed-off-by: Rodrigo Vivi Reviewed-by: Clinton Taylor --- intel/intel_chipset.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index e6b49d7..37579c6 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -237,6 +237,12 @@ #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A +#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 +#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 +#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 +#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 +#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 +#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -501,12 +507,20 @@ IS_GEN8(dev) || \ IS_GEN9(dev)) +#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) + #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid)) +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ + IS_CNL_Y(devid)) #define IS_GEN10(devid) (IS_CANNONLAKE(devid))