From patchwork Thu Jul 27 16:42:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9867329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF9C160382 for ; Thu, 27 Jul 2017 16:43:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C21D328849 for ; Thu, 27 Jul 2017 16:43:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B6F4328847; Thu, 27 Jul 2017 16:43:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7AB6328853 for ; Thu, 27 Jul 2017 16:43:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99C4C6EE1D; Thu, 27 Jul 2017 16:42:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 444216EE13; Thu, 27 Jul 2017 16:42:54 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 304A960A07; Thu, 27 Jul 2017 16:42:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501173774; bh=6bzxYh++Lik4Fie+NEnENH2i4nC4zVMOGznXKzQ9WDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KIkUXLs7kpQRI2NPaQXGAoRqF8j6BL52Uiy7I7oZU4q/N1ZpmRX6Knt8VFjKF8IUl IMQt97GeJPrRj31EjxnqqyGmCrueMR124nttJ1ZLfQ6Tx+lPqiabjO4coZMCrM7LHC OV0atUyKXWuF6ajEODz+9Gk35a9HsO39qLzBeWjA= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 81C35609D1; Thu, 27 Jul 2017 16:42:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501173773; bh=6bzxYh++Lik4Fie+NEnENH2i4nC4zVMOGznXKzQ9WDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KdyZMSyxpkzNaxy33S46ZPfrTckWt7eXcNGT6KetDoPFBsH5Xpd7TOaGF8WOrEzmB QiJMKkkjmB1XOoMgw2AErxj4+NtVx3wCd7na/2Ikta/n6vXO9fL619/Yn+SuAom/24 gQvb/zHNGr8kI7zgmwUIJLDmD+oQIoKre9Rs9k6Q= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 81C35609D1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 03/17] drm/msm: Turn off hardware clock gating before reading A5XX registers Date: Thu, 27 Jul 2017 10:42:32 -0600 Message-Id: <1501173766-24856-4-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501173766-24856-1-git-send-email-jcrouse@codeaurora.org> References: <1501173766-24856-1-git-send-email-jcrouse@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP On A5XX GPU hardware clock gating needs to be turned off before reading certain GPU registers via AHB. Turn off HWCG before calling adreno_show() to safely dump all the registers without a system hang. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index c1f8c20..33763b0 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -995,7 +995,14 @@ static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m) { seq_printf(m, "status: %08x\n", gpu_read(gpu, REG_A5XX_RBBM_STATUS)); + + /* + * Temporarily disable hardware clock gating before going into + * adreno_show to avoid issues while reading the registers + */ + a5xx_set_hwcg(gpu, false); adreno_show(gpu, m); + a5xx_set_hwcg(gpu, true); } #endif