From patchwork Tue Aug 22 18:42:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: John Stultz X-Patchwork-Id: 9915909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3B504603F9 for ; Tue, 22 Aug 2017 18:42:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 334492891A for ; Tue, 22 Aug 2017 18:42:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2809D28928; Tue, 22 Aug 2017 18:42:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7D29D28926 for ; Tue, 22 Aug 2017 18:42:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7804E6E3E0; Tue, 22 Aug 2017 18:42:36 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pg0-x231.google.com (mail-pg0-x231.google.com [IPv6:2607:f8b0:400e:c05::231]) by gabe.freedesktop.org (Postfix) with ESMTPS id 788E56E3E0 for ; Tue, 22 Aug 2017 18:42:34 +0000 (UTC) Received: by mail-pg0-x231.google.com with SMTP id i12so118390136pgr.3 for ; Tue, 22 Aug 2017 11:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=osm0FDGsoJqTUvt+00iuRoeOuSno3NPbGZQ36BfBv9Q=; b=BMyUfFiEeEkrzSlmmTAaqmLQRh3AKwXpvLxLCjXn0SR1E+OPehz3PhD4zTEIqRu5TR XtJr17fx794JDoMeREy7oypQr9V/o+zlIfo1Jh09BsxrKp2HqHVMB2sDU9IfciD3giwS HXRmGaO+qigV+/wScpNiWd0STskfQtxVxIAGE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=osm0FDGsoJqTUvt+00iuRoeOuSno3NPbGZQ36BfBv9Q=; b=IuNV3FPgwI/F+39+MPInOdLpoNR5CcD7Jsj6IEl7vne86hSc25E0uQbf+DUvzWRRFH /HHJkrQxMOdTMIxpxUM7/NeHdNonoi/GZmMcmtG8Npp+G+YD1xDDGvAeHJxqj2Ami78Q loj2vUJfALl2jxGCM/nHIkdTNAi41coEQBurFGVR/1YI419jxPVyq2Jp2wLkvtWJX2Z3 78WOiw9vWn7PKuUcXLEq1N9LN9yESUCen99azS5u099/nGDfj7Li5PhMf2ZKFBta2kLv TuDr7n5+wDwSwdR4p0nyRbe2pWGdZzRZmdvzNSaaFSvmBXUNm4lMl/MjVaNNvUIlgV76 WcqQ== X-Gm-Message-State: AHYfb5jRVImKWFjo6nejnpi1+y+hiByZIy15Wa2rbn4L9XyvbdcVim2K IEdlZBmCgXaX4M89 X-Received: by 10.84.167.2 with SMTP id c2mr68271plb.367.1503427353944; Tue, 22 Aug 2017 11:42:33 -0700 (PDT) Received: from localhost.localdomain ([2601:1c2:1002:83f0:4e72:b9ff:fe99:466a]) by smtp.gmail.com with ESMTPSA id x74sm12120995pfa.54.2017.08.22.11.42.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Aug 2017 11:42:32 -0700 (PDT) From: John Stultz To: lkml Subject: [PATCH v5] drm: kirin: Add mode_valid logic to avoid mode clocks we can't generate Date: Tue, 22 Aug 2017 11:42:26 -0700 Message-Id: <1503427346-17667-1-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: Jose Abreu , Chen Feng , Xinwei Kong , Xinliang Liu , dri-devel@lists.freedesktop.org, Rongrong Zou , Daniel Vetter X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently the hikey dsi logic cannot generate accurate byte clocks values for all pixel clock values. Thus if a mode clock is selected that cannot match the calculated byte clock, the device will boot with a blank screen. This patch uses the new mode_valid callback (many thanks to Jose Abreu for upstreaming it!) to ensure we don't select modes we cannot generate. Also, since the ade crtc code will adjust the mode in mode_set, this patch also adds a mode_fixup callback which we use to make sure we are validating the mode clock that will eventually be used. Cc: Daniel Vetter Cc: Jani Nikula Cc: Sean Paul Cc: David Airlie Cc: Rob Clark Cc: Xinliang Liu Cc: Xinliang Liu Cc: Rongrong Zou Cc: Xinwei Kong Cc: Chen Feng Cc: Jose Abreu Cc: Archit Taneja Cc: dri-devel@lists.freedesktop.org Reviewed-by: Sean Paul Signed-off-by: John Stultz Reviewed-by: Xinliang Liu ​ --- v2: Reworked to calculate if modeclock matches the phy's byteclock, rather then using a whitelist of known modes. v3: Reworked to check across all possible crtcs (even though for us there is only one), and use mode_fixup instead of a custom function, as suggested by Jose and Daniel. v4: Fixes and improved error handling as suggested by Jose. v5: Small typo fix noted by Sean --- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 67 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 14 ++++++ 2 files changed, 81 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index f77dcfa..b4c7af3 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -603,6 +603,72 @@ static void dsi_encoder_enable(struct drm_encoder *encoder) dsi->enable = true; } +static enum drm_mode_status dsi_encoder_phy_mode_valid( + struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct mipi_phy_params phy; + u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + u32 req_kHz, act_kHz, lane_byte_clk_kHz; + + /* Calculate the lane byte clk using the adjusted mode clk */ + memset(&phy, 0, sizeof(phy)); + req_kHz = mode->clock * bpp / dsi->lanes; + act_kHz = dsi_calc_phy_rate(req_kHz, &phy); + lane_byte_clk_kHz = act_kHz / 8; + + DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...", + mode->hdisplay, mode->vdisplay, bpp, + drm_mode_vrefresh(mode), mode->clock); + + /* + * Make sure the adjusted mode clock and the lane byte clk + * have a common denominator base frequency + */ + if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) { + DRM_DEBUG_DRIVER("OK!\n"); + return MODE_OK; + } + + DRM_DEBUG_DRIVER("BAD!\n"); + return MODE_BAD; +} + +static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) + +{ + const struct drm_crtc_helper_funcs *crtc_funcs = NULL; + struct drm_crtc *crtc = NULL; + struct drm_display_mode adj_mode; + enum drm_mode_status ret; + + /* + * The crtc might adjust the mode, so go through the + * possible crtcs (technically just one) and call + * mode_fixup to figure out the adjusted mode before we + * validate it. + */ + drm_for_each_crtc(crtc, encoder->dev) { + /* + * reset adj_mode to the mode value each time, + * so we don't adjust the mode twice + */ + drm_mode_copy(&adj_mode, mode); + + crtc_funcs = crtc->helper_private; + if (crtc_funcs && crtc_funcs->mode_fixup) + if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode)) + return MODE_BAD; + + ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode); + if (ret != MODE_OK) + return ret; + } + return MODE_OK; +} + static void dsi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -622,6 +688,7 @@ static int dsi_encoder_atomic_check(struct drm_encoder *encoder, static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { .atomic_check = dsi_encoder_atomic_check, + .mode_valid = dsi_encoder_mode_valid, .mode_set = dsi_encoder_mode_set, .enable = dsi_encoder_enable, .disable = dsi_encoder_disable diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index c96c228..dec7f4e 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -178,6 +178,19 @@ static void ade_init(struct ade_hw_ctx *ctx) FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); } +static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + adjusted_mode->clock = + clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; + return true; +} + + static void ade_set_pix_clk(struct ade_hw_ctx *ctx, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -555,6 +568,7 @@ static void ade_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { .enable = ade_crtc_enable, .disable = ade_crtc_disable, + .mode_fixup = ade_crtc_mode_fixup, .mode_set_nofb = ade_crtc_mode_set_nofb, .atomic_begin = ade_crtc_atomic_begin, .atomic_flush = ade_crtc_atomic_flush,