From patchwork Wed Jul 9 15:25:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Br=C3=BCns?= X-Patchwork-Id: 4520361 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B76C1BEEAA for ; Thu, 10 Jul 2014 01:53:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C95F32026F for ; Thu, 10 Jul 2014 01:53:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C99122028D for ; Thu, 10 Jul 2014 01:53:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D66F76E0F9; Wed, 9 Jul 2014 18:53:49 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx-out-2.rwth-aachen.de (mx-out-2.rwth-aachen.de [134.130.5.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 266BB6E0E2 for ; Wed, 9 Jul 2014 08:25:20 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.01,631,1400018400"; d="scan'208";a="251355473" Received: from hub2.rwth-ad.de (HELO mail.rwth-aachen.de) ([134.130.26.143]) by mx-2.rz.rwth-aachen.de with ESMTP; 09 Jul 2014 17:25:13 +0200 Received: from MBX7.rwth-ad.de ([fe80::24c4:c21d:c08d:1e9c]) by HUB2.rwth-ad.de ([fe80::8977:fb2f:b373:acc5%20]) with mapi id 14.03.0181.006; Wed, 9 Jul 2014 17:25:13 +0200 From: =?iso-8859-1?Q?Br=FCns=2C_Stefan?= To: "dri-devel@lists.freedesktop.org" Subject: [PATCH] radeon: add HDMI/DP sink description to ELD like data Thread-Topic: [PATCH] radeon: add HDMI/DP sink description to ELD like data Thread-Index: AQHPm4n6155SagPX3EeXnoC7SuP2tQ== Date: Wed, 9 Jul 2014 15:25:13 +0000 Message-ID: <1505916.YJMHg1Tr1f@sbruens-linux> Accept-Language: en-US, de-DE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [62.153.130.147] x-pmwin-version: 3.1.1.0 Content-ID: MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 09 Jul 2014 18:53:49 -0700 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Provide monitor name and product/manufacturer id to alsa hda driver. The output matches the fglrx settings, short of the port_id. As the latter is not standardized, leave it out for now. Corresponding alsa code is already in place. Signed-off-by: Stefan Brüns --- The fglrx register settings where retrieved using Rafal Mileckis gdb script. After applying the patch fglrx and radeon register settings for sink info match, short of the port_id. Regarding port id, see comment by Takashi Iwai, 14 Nov 2013: http://www.spinics.net/linux/fedora/alsa-user/msg12453.html and RFC by Stephen Warren (NVidia), 25 May 2011: http://lists.freedesktop.org/pipermail/xorg/2011-May/052893.html drivers/gpu/drm/radeon/dce6_afmt.c | 67 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/evergreen_hdmi.c | 2 + 2 files changed, 69 insertions(+) diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c index 0a65dc7..1adf95a 100644 --- a/drivers/gpu/drm/radeon/dce6_afmt.c +++ b/drivers/gpu/drm/radeon/dce6_afmt.c @@ -273,6 +273,73 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) kfree(sads); } +void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder) +{ + struct radeon_device *rdev = encoder->dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + struct drm_connector *connector; + u32 tmp = 0, offset; + char description[18]; + uint8_t *eld; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + offset = dig->afmt->pin->offset; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) + break; + } + + if (!connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (!connector->eld[0]) { + DRM_ERROR("Connector has no ELD\n"); + return; + } + + eld = connector->eld; + + tmp = MANUFACTURER_ID(eld[16]<<8 | eld[17]) | PRODUCT_ID(eld[18]<<8 | eld[19]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0, tmp); + + tmp = SINK_DESCRIPTION_LEN(strlen(&eld[20])) + 1; + tmp = (tmp > 19) ? 19 : tmp; + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1, tmp); + + strncpy(description, &eld[20], 18); + + tmp = PORT_ID0(0x1); + //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2, tmp); + + tmp = PORT_ID1(0x100); + //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3, tmp); + + tmp = DESCRIPTION0(description[0]) | DESCRIPTION1(description[1]) | + DESCRIPTION2(description[2]) | DESCRIPTION3(description[3]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4, tmp); + + tmp = DESCRIPTION4(description[4]) | DESCRIPTION5(description[5]) | + DESCRIPTION6(description[6]) | DESCRIPTION7(description[7]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5, tmp); + + tmp = DESCRIPTION8(description[8]) | DESCRIPTION9(description[9]) | + DESCRIPTION10(description[10]) | DESCRIPTION11(description[11]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6, tmp); + + tmp = DESCRIPTION12(description[12]) | DESCRIPTION13(description[13]) | + DESCRIPTION14(description[14]) | DESCRIPTION15(description[15]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7, tmp); + + tmp = DESCRIPTION16(description[16]) | DESCRIPTION17(description[17]); + WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8, tmp); +} + static int dce6_audio_chipset_supported(struct radeon_device *rdev) { return !ASIC_IS_NODCE(rdev); diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 1ec0e6e..b04ec3b 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -37,6 +37,7 @@ extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); extern void dce6_afmt_select_pin(struct drm_encoder *encoder); extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, struct drm_display_mode *mode); +extern void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder); /* * update the N and CTS parameters for a given pixel clock rate @@ -425,6 +426,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode dce6_afmt_select_pin(encoder); dce6_afmt_write_sad_regs(encoder); dce6_afmt_write_latency_fields(encoder, mode); + dce6_afmt_write_sinkinfo(encoder); } else { evergreen_hdmi_write_sad_regs(encoder); dce4_afmt_write_latency_fields(encoder, mode);