From patchwork Thu Oct 26 16:09:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 10028603 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4060260375 for ; Thu, 26 Oct 2017 16:10:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2EFCE28EB0 for ; Thu, 26 Oct 2017 16:10:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 23B8328ECC; Thu, 26 Oct 2017 16:10:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 69C4428EB0 for ; Thu, 26 Oct 2017 16:10:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADD756E826; Thu, 26 Oct 2017 16:10:08 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9AA256E826 for ; Thu, 26 Oct 2017 16:10:07 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9QG4PSg016972; Thu, 26 Oct 2017 18:09:56 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2dua1kjvyn-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Oct 2017 18:09:56 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3EAF534; Thu, 26 Oct 2017 16:09:54 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 10D922B4C; Thu, 26 Oct 2017 16:09:54 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.352.0; Thu, 26 Oct 2017 18:09:53 +0200 Received: from localhost (10.201.23.32) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Thu, 26 Oct 2017 18:09:53 +0200 From: Philippe Cornu To: Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , Philippe Cornu , Philipp Zabel , Benjamin Gaignard , Bhumika Goyal , , Subject: [PATCH] drm/bridge/synopsys: dsi: add optional pixel clock Date: Thu, 26 Oct 2017 18:09:35 +0200 Message-ID: <1509034175-23767-1-git-send-email-philippe.cornu@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-26_05:, , signatures=0 Cc: Alexandre Torgue , Fabien Dessenne , Yannick Fertre , Maxime Coquelin , Mickael Reulier , Vincent Abriou , Gabriel Fernandez , Ludovic Barre X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The pixel clock is optional. When available, it offers a better preciseness for timing computations. Signed-off-by: Philippe Cornu --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index d9cca4f..8b3787d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -225,6 +225,7 @@ struct dw_mipi_dsi { void __iomem *base; struct clk *pclk; + struct clk *px_clk; unsigned int lane_mbps; /* per lane */ u32 channel; @@ -753,24 +754,28 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; void *priv_data = dsi->plat_data->priv_data; + struct drm_display_mode px_clk_mode = *mode; int ret; clk_prepare_enable(dsi->pclk); - ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, + if (dsi->px_clk) + px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000; + + ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags, dsi->lanes, dsi->format, &dsi->lane_mbps); if (ret) DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); pm_runtime_get_sync(dsi->dev); dw_mipi_dsi_init(dsi); - dw_mipi_dsi_dpi_config(dsi, mode); + dw_mipi_dsi_dpi_config(dsi, &px_clk_mode); dw_mipi_dsi_packet_handler_config(dsi); dw_mipi_dsi_video_mode_config(dsi); - dw_mipi_dsi_video_packet_config(dsi, mode); + dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode); dw_mipi_dsi_command_mode_config(dsi); - dw_mipi_dsi_line_timer_config(dsi, mode); - dw_mipi_dsi_vertical_timing_config(dsi, mode); + dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode); + dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode); dw_mipi_dsi_dphy_init(dsi); dw_mipi_dsi_dphy_timing_config(dsi); @@ -784,7 +789,7 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, dw_mipi_dsi_dphy_enable(dsi); - dw_mipi_dsi_wait_for_two_frames(mode); + dw_mipi_dsi_wait_for_two_frames(&px_clk_mode); /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ dw_mipi_dsi_set_mode(dsi, 0); @@ -878,6 +883,13 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) return ERR_PTR(ret); } + dsi->px_clk = devm_clk_get(dev, "px_clk"); + if (IS_ERR(dsi->px_clk)) { + ret = PTR_ERR(dsi->px_clk); + dev_dbg(dev, "Unable to get optional px_clk: %d\n", ret); + dsi->px_clk = NULL; + } + /* * Note that the reset was not defined in the initial device tree, so * we have to be prepared for it not being found.