| Message ID | 1521237059-37117-3-git-send-email-stschake@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Stefan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on v4.16-rc4]
[also build test WARNING on next-20180316]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Stefan-Schake/drm-vc4-Atomic-color-management-support/20180318-120701
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sh
All warnings (new ones prefixed by >>):
drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_gamma_lut':
drivers/gpu/drm/vc4/vc4_crtc.c:305:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
struct drm_color_lut *lut = crtc->state->gamma_lut->data;
^~~~
drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_ctm':
drivers/gpu/drm/vc4/vc4_crtc.c:340:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
struct drm_color_ctm *ctm = crtc->state->ctm->data;
^~~~
In file included from include/linux/fb.h:17:0,
from include/drm/drm_crtc.h:31,
from include/drm/drm_atomic.h:31,
from drivers/gpu/drm/vc4/vc4_crtc.c:35:
drivers/gpu/drm/vc4/vc4_crtc.c:342:12: error: 'SCALER_OLEDCOEF2' undeclared (first use in this function); did you mean 'SCALER_DISPCTRL2'?
HVS_WRITE(SCALER_OLEDCOEF2,
^
arch/sh/include/asm/io.h:31:71: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:342:12: note: each undeclared identifier is reported only once for each function it appears in
HVS_WRITE(SCALER_OLEDCOEF2,
^
arch/sh/include/asm/io.h:31:71: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_CSC0_COEF_CR_OFS_SHIFT'?
SCALER_OLEDCOEF2_R_TO_R) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF2_R_TO_R) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF2_R_TO_G) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
SCALER_OLEDCOEF2_R_TO_G) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_SHIFT'?
SCALER_OLEDCOEF2_R_TO_B));
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_MASK'?
SCALER_OLEDCOEF2_R_TO_B));
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF2,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:349:12: error: 'SCALER_OLEDCOEF1' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2'?
HVS_WRITE(SCALER_OLEDCOEF1,
^
arch/sh/include/asm/io.h:31:71: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:349:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF1,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF1_G_TO_R) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:349:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF1,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
SCALER_OLEDCOEF1_G_TO_R) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:349:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF1,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_SHIFT'?
SCALER_OLEDCOEF1_G_TO_G) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_drv.h:301:32: note: in expansion of macro 'writel'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:349:2: note: in expansion of macro 'HVS_WRITE'
HVS_WRITE(SCALER_OLEDCOEF1,
^~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:352:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_MASK'?
SCALER_OLEDCOEF1_G_TO_G) |
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
vim +/HVS_WRITE +342 drivers/gpu/drm/vc4/vc4_crtc.c
333
334 static void
335 vc4_crtc_update_ctm(struct drm_crtc *crtc)
336 {
337 struct drm_device *dev = crtc->dev;
338 struct vc4_dev *vc4 = to_vc4_dev(dev);
339 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
340 struct drm_color_ctm *ctm = crtc->state->ctm->data;
341
> 342 HVS_WRITE(SCALER_OLEDCOEF2,
343 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
344 SCALER_OLEDCOEF2_R_TO_R) |
345 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
346 SCALER_OLEDCOEF2_R_TO_G) |
347 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
348 SCALER_OLEDCOEF2_R_TO_B));
349 HVS_WRITE(SCALER_OLEDCOEF1,
350 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
351 SCALER_OLEDCOEF1_G_TO_R) |
352 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
353 SCALER_OLEDCOEF1_G_TO_G) |
354 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]),
355 SCALER_OLEDCOEF1_G_TO_B));
356 HVS_WRITE(SCALER_OLEDCOEF0,
357 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[2]),
358 SCALER_OLEDCOEF0_B_TO_R) |
359 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[5]),
360 SCALER_OLEDCOEF0_B_TO_G) |
361 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[8]),
362 SCALER_OLEDCOEF0_B_TO_B));
363
364 /* Channel is 0-based but for DISPFIFO, 0 means disabled. */
365 HVS_WRITE(SCALER_OLEDOFFS, VC4_SET_FIELD(vc4_crtc->channel + 1,
366 SCALER_OLEDOFFS_DISPFIFO));
367 }
368
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Stefan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.16-rc4]
[also build test ERROR on next-20180316]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Stefan-Schake/drm-vc4-Atomic-color-management-support/20180318-120701
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_gamma_lut':
drivers/gpu/drm/vc4/vc4_crtc.c:305:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
struct drm_color_lut *lut = crtc->state->gamma_lut->data;
^~~~
drivers/gpu/drm/vc4/vc4_crtc.c: In function 'vc4_crtc_update_ctm':
drivers/gpu/drm/vc4/vc4_crtc.c:340:30: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
struct drm_color_ctm *ctm = crtc->state->ctm->data;
^~~~
In file included from drivers/gpu/drm/vc4/vc4_crtc.c:42:0:
>> drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_CSC0_COEF_CR_OFS_SHIFT'?
SCALER_OLEDCOEF2_R_TO_R) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
^~~~~~~~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:344:5: note: each undeclared identifier is reported only once for each function it appears in
SCALER_OLEDCOEF2_R_TO_R) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:344:5: error: 'SCALER_OLEDCOEF2_R_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF2_R_TO_R) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:343:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF2_R_TO_G) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:346:5: error: 'SCALER_OLEDCOEF2_R_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
SCALER_OLEDCOEF2_R_TO_G) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:345:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_SHIFT'?
SCALER_OLEDCOEF2_R_TO_B));
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:348:5: error: 'SCALER_OLEDCOEF2_R_TO_B_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_G_MASK'?
SCALER_OLEDCOEF2_R_TO_B));
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:347:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:342:12: error: 'SCALER_OLEDCOEF2' undeclared (first use in this function); did you mean 'SCALER_DISPCTRL2'?
HVS_WRITE(SCALER_OLEDCOEF2,
^
drivers/gpu/drm/vc4/vc4_drv.h:301:61: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_SHIFT'?
SCALER_OLEDCOEF1_G_TO_R) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:351:5: error: 'SCALER_OLEDCOEF1_G_TO_R_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF2_R_TO_R_MASK'?
SCALER_OLEDCOEF1_G_TO_R) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:350:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_SHIFT'?
SCALER_OLEDCOEF1_G_TO_G) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
drivers/gpu/drm/vc4/vc4_crtc.c:352:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:353:5: error: 'SCALER_OLEDCOEF1_G_TO_G_MASK' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_R_MASK'?
SCALER_OLEDCOEF1_G_TO_G) |
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
>> drivers/gpu/drm/vc4/vc4_regs.h:19:3: note: in expansion of macro 'WARN_ON'
WARN_ON((fieldval & ~field##_MASK) != 0); \
^~~~~~~
drivers/gpu/drm/vc4/vc4_crtc.c:352:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
^~~~~~~~~~~~~
>> drivers/gpu/drm/vc4/vc4_crtc.c:355:5: error: 'SCALER_OLEDCOEF1_G_TO_B_SHIFT' undeclared (first use in this function); did you mean 'SCALER_OLEDCOEF1_G_TO_G_SHIFT'?
SCALER_OLEDCOEF1_G_TO_B));
^
drivers/gpu/drm/vc4/vc4_drv.h:301:39: note: in definition of macro 'HVS_WRITE'
#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
^~~
drivers/gpu/drm/vc4/vc4_crtc.c:354:5: note: in expansion of macro 'VC4_SET_FIELD'
VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]),
^~~~~~~~~~~~~
vim +344 drivers/gpu/drm/vc4/vc4_crtc.c
300
301 static void
302 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
303 {
304 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
> 305 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
306 u32 length = crtc->state->gamma_lut->length / sizeof(*lut);
307 u32 i;
308
309 for (i = 0; i < length; i++) {
310 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
311 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
312 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
313 }
314
315 vc4_crtc_lut_load(crtc);
316 }
317
318 /* Converts a DRM S31.32 value to the HW S0.9 format. */
319 static u16 vc4_crtc_s31_32_to_s0_9(u64 in)
320 {
321 u16 r;
322
323 /* Sign bit. */
324 r = in & BIT_ULL(63) ? BIT(9) : 0;
325 /* We have zero integer bits so we can only saturate here. */
326 if ((in & GENMASK_ULL(62, 32)) > 0)
327 r |= GENMASK(8, 0);
328 /* Otherwise take the 9 most important fractional bits. */
329 else
330 r |= (in >> 22) & GENMASK(8, 0);
331 return r;
332 }
333
334 static void
335 vc4_crtc_update_ctm(struct drm_crtc *crtc)
336 {
337 struct drm_device *dev = crtc->dev;
338 struct vc4_dev *vc4 = to_vc4_dev(dev);
339 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
340 struct drm_color_ctm *ctm = crtc->state->ctm->data;
341
> 342 HVS_WRITE(SCALER_OLEDCOEF2,
> 343 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]),
> 344 SCALER_OLEDCOEF2_R_TO_R) |
> 345 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]),
> 346 SCALER_OLEDCOEF2_R_TO_G) |
> 347 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]),
> 348 SCALER_OLEDCOEF2_R_TO_B));
> 349 HVS_WRITE(SCALER_OLEDCOEF1,
> 350 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]),
> 351 SCALER_OLEDCOEF1_G_TO_R) |
> 352 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]),
> 353 SCALER_OLEDCOEF1_G_TO_G) |
> 354 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]),
> 355 SCALER_OLEDCOEF1_G_TO_B));
> 356 HVS_WRITE(SCALER_OLEDCOEF0,
> 357 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[2]),
> 358 SCALER_OLEDCOEF0_B_TO_R) |
> 359 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[5]),
> 360 SCALER_OLEDCOEF0_B_TO_G) |
> 361 VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[8]),
> 362 SCALER_OLEDCOEF0_B_TO_B));
363
364 /* Channel is 0-based but for DISPFIFO, 0 means disabled. */
> 365 HVS_WRITE(SCALER_OLEDOFFS, VC4_SET_FIELD(vc4_crtc->channel + 1,
> 366 SCALER_OLEDOFFS_DISPFIFO));
367 }
368
369 /* Check if the CTM contains valid input.
370 *
371 * DRM exposes CTM with S31.32 scalars, but the HW only supports S0.9.
372 * We don't allow integer values >1, and 1 only without fractional part
373 * to handle the common 1.0 value.
374 */
375 static int vc4_crtc_atomic_check_ctm(struct drm_crtc_state *state)
376 {
> 377 struct drm_color_ctm *ctm = state->ctm->data;
378 u32 i;
379
380 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
381 u64 val = ctm->matrix[i];
382
383 val &= ~BIT_ULL(63);
384 if ((val >> 32) > 1)
385 return -EINVAL;
386 if ((val >> 32) == 1 && (val & GENMASK_ULL(31, 0)) != 0)
387 return -EINVAL;
388 }
389
390 return 0;
391 }
392
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On Fri, Mar 16, 2018 at 10:50:58PM +0100, Stefan Schake wrote: > The hardware supports a CTM with S0.9 values. We therefore only allow > a value of 1.0 or fractional only and reject all others with integer > parts. This restriction is mostly inconsequential in practice since > commonly used transformation matrices have all scalars <= 1.0. > > Signed-off-by: Stefan Schake <stschake@gmail.com> > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 99 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 96 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index 8d71098..5c83fd2 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -315,6 +315,81 @@ vc4_crtc_update_gamma_lut(struct drm_crtc *crtc) > vc4_crtc_lut_load(crtc); > } > > +/* Converts a DRM S31.32 value to the HW S0.9 format. */ > +static u16 vc4_crtc_s31_32_to_s0_9(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(9) : 0; > + /* We have zero integer bits so we can only saturate here. */ > + if ((in & GENMASK_ULL(62, 32)) > 0) > + r |= GENMASK(8, 0); > + /* Otherwise take the 9 most important fractional bits. */ > + else > + r |= (in >> 22) & GENMASK(8, 0); > + return r; > +} > + > +static void > +vc4_crtc_update_ctm(struct drm_crtc *crtc) > +{ > + struct drm_device *dev = crtc->dev; > + struct vc4_dev *vc4 = to_vc4_dev(dev); > + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > + struct drm_color_ctm *ctm = crtc->state->ctm->data; > + > + HVS_WRITE(SCALER_OLEDCOEF2, > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]), > + SCALER_OLEDCOEF2_R_TO_R) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]), > + SCALER_OLEDCOEF2_R_TO_G) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]), > + SCALER_OLEDCOEF2_R_TO_B)); > + HVS_WRITE(SCALER_OLEDCOEF1, > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]), > + SCALER_OLEDCOEF1_G_TO_R) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]), > + SCALER_OLEDCOEF1_G_TO_G) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]), > + SCALER_OLEDCOEF1_G_TO_B)); > + HVS_WRITE(SCALER_OLEDCOEF0, > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[2]), > + SCALER_OLEDCOEF0_B_TO_R) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[5]), > + SCALER_OLEDCOEF0_B_TO_G) | > + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[8]), > + SCALER_OLEDCOEF0_B_TO_B)); > + > + /* Channel is 0-based but for DISPFIFO, 0 means disabled. */ > + HVS_WRITE(SCALER_OLEDOFFS, VC4_SET_FIELD(vc4_crtc->channel + 1, > + SCALER_OLEDOFFS_DISPFIFO)); > +} > + > +/* Check if the CTM contains valid input. > + * > + * DRM exposes CTM with S31.32 scalars, but the HW only supports S0.9. > + * We don't allow integer values >1, and 1 only without fractional part > + * to handle the common 1.0 value. > + */ > +static int vc4_crtc_atomic_check_ctm(struct drm_crtc_state *state) > +{ > + struct drm_color_ctm *ctm = state->ctm->data; > + u32 i; > + > + for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { > + u64 val = ctm->matrix[i]; > + > + val &= ~BIT_ULL(63); > + if ((val >> 32) > 1) > + return -EINVAL; > + if ((val >> 32) == 1 && (val & GENMASK_ULL(31, 0)) != 0) > + return -EINVAL; 'val > BIT_ULL(32)' ? > + } > + > + return 0; > +} > + > static u32 vc4_get_fifo_full_level(u32 format) > { > static const u32 fifo_len_bytes = 64; > @@ -621,6 +696,15 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc, > if (hweight32(state->connector_mask) > 1) > return -EINVAL; > > + if (state->ctm) { > + /* The CTM hardware has no integer bits, so we check > + * and reject scalars >1.0 that we have no chance of > + * approximating. > + */ > + if (vc4_crtc_atomic_check_ctm(state)) > + return -EINVAL; > + } > + > drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) > dlist_count += vc4_plane_dlist_size(plane_state); > > @@ -697,8 +781,17 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, > if (crtc->state->active && old_state->active) > vc4_crtc_update_dlist(crtc); > > - if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) > - vc4_crtc_update_gamma_lut(crtc); > + if (crtc->state->color_mgmt_changed) { > + if (crtc->state->gamma_lut) > + vc4_crtc_update_gamma_lut(crtc); > + > + if (crtc->state->ctm) > + vc4_crtc_update_ctm(crtc); > + /* We are transitioning to CTM disabled. */ > + else if (old_state->ctm) > + HVS_WRITE(SCALER_OLEDOFFS, > + VC4_SET_FIELD(0, SCALER_OLEDOFFS_DISPFIFO)); > + } > > if (debug_dump_regs) { > DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); > @@ -1036,7 +1129,7 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) > primary_plane->crtc = crtc; > vc4_crtc->channel = vc4_crtc->data->hvs_channel; > drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); > - drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); > + drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); > > /* Set up some arbitrary number of planes. We're not limited > * by a set number of physical registers, just the space in > -- > 2.7.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 8d71098..5c83fd2 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -315,6 +315,81 @@ vc4_crtc_update_gamma_lut(struct drm_crtc *crtc) vc4_crtc_lut_load(crtc); } +/* Converts a DRM S31.32 value to the HW S0.9 format. */ +static u16 vc4_crtc_s31_32_to_s0_9(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(9) : 0; + /* We have zero integer bits so we can only saturate here. */ + if ((in & GENMASK_ULL(62, 32)) > 0) + r |= GENMASK(8, 0); + /* Otherwise take the 9 most important fractional bits. */ + else + r |= (in >> 22) & GENMASK(8, 0); + return r; +} + +static void +vc4_crtc_update_ctm(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_color_ctm *ctm = crtc->state->ctm->data; + + HVS_WRITE(SCALER_OLEDCOEF2, + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[0]), + SCALER_OLEDCOEF2_R_TO_R) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[3]), + SCALER_OLEDCOEF2_R_TO_G) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[6]), + SCALER_OLEDCOEF2_R_TO_B)); + HVS_WRITE(SCALER_OLEDCOEF1, + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[1]), + SCALER_OLEDCOEF1_G_TO_R) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[4]), + SCALER_OLEDCOEF1_G_TO_G) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[7]), + SCALER_OLEDCOEF1_G_TO_B)); + HVS_WRITE(SCALER_OLEDCOEF0, + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[2]), + SCALER_OLEDCOEF0_B_TO_R) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[5]), + SCALER_OLEDCOEF0_B_TO_G) | + VC4_SET_FIELD(vc4_crtc_s31_32_to_s0_9(ctm->matrix[8]), + SCALER_OLEDCOEF0_B_TO_B)); + + /* Channel is 0-based but for DISPFIFO, 0 means disabled. */ + HVS_WRITE(SCALER_OLEDOFFS, VC4_SET_FIELD(vc4_crtc->channel + 1, + SCALER_OLEDOFFS_DISPFIFO)); +} + +/* Check if the CTM contains valid input. + * + * DRM exposes CTM with S31.32 scalars, but the HW only supports S0.9. + * We don't allow integer values >1, and 1 only without fractional part + * to handle the common 1.0 value. + */ +static int vc4_crtc_atomic_check_ctm(struct drm_crtc_state *state) +{ + struct drm_color_ctm *ctm = state->ctm->data; + u32 i; + + for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { + u64 val = ctm->matrix[i]; + + val &= ~BIT_ULL(63); + if ((val >> 32) > 1) + return -EINVAL; + if ((val >> 32) == 1 && (val & GENMASK_ULL(31, 0)) != 0) + return -EINVAL; + } + + return 0; +} + static u32 vc4_get_fifo_full_level(u32 format) { static const u32 fifo_len_bytes = 64; @@ -621,6 +696,15 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc, if (hweight32(state->connector_mask) > 1) return -EINVAL; + if (state->ctm) { + /* The CTM hardware has no integer bits, so we check + * and reject scalars >1.0 that we have no chance of + * approximating. + */ + if (vc4_crtc_atomic_check_ctm(state)) + return -EINVAL; + } + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) dlist_count += vc4_plane_dlist_size(plane_state); @@ -697,8 +781,17 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, if (crtc->state->active && old_state->active) vc4_crtc_update_dlist(crtc); - if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) - vc4_crtc_update_gamma_lut(crtc); + if (crtc->state->color_mgmt_changed) { + if (crtc->state->gamma_lut) + vc4_crtc_update_gamma_lut(crtc); + + if (crtc->state->ctm) + vc4_crtc_update_ctm(crtc); + /* We are transitioning to CTM disabled. */ + else if (old_state->ctm) + HVS_WRITE(SCALER_OLEDOFFS, + VC4_SET_FIELD(0, SCALER_OLEDOFFS_DISPFIFO)); + } if (debug_dump_regs) { DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); @@ -1036,7 +1129,7 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) primary_plane->crtc = crtc; vc4_crtc->channel = vc4_crtc->data->hvs_channel; drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); - drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); + drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); /* Set up some arbitrary number of planes. We're not limited * by a set number of physical registers, just the space in
The hardware supports a CTM with S0.9 values. We therefore only allow a value of 1.0 or fractional only and reject all others with integer parts. This restriction is mostly inconsequential in practice since commonly used transformation matrices have all scalars <= 1.0. Signed-off-by: Stefan Schake <stschake@gmail.com> --- drivers/gpu/drm/vc4/vc4_crtc.c | 99 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 3 deletions(-)