Message ID | 1539034953-11274-3-git-send-email-dkos@cadence.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Mon, 8 Oct 2018 23:43:27 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Mon, 8 Oct 2018 23:43:27 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id w98LhJHG013168; Mon, 8 Oct 2018 22:43:19 +0100 Received: (from dkos@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id w98LhJrT013166; Mon, 8 Oct 2018 22:43:19 +0100 From: Damian Kos <dkos@cadence.com> To: David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>, "Mark Rutland" <mark.rutland@arm.com>, Archit Taneja <architt@codeaurora.org>, Andrzej Hajda <a.hajda@samsung.com>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Gustavo Padovan <gustavo@padovan.org>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Sean Paul <sean@poorly.run>, Sandy Huang <hjc@rock-chips.com>, =?utf-8?q?He?= =?utf-8?q?iko_St=C3=BCbner?= <heiko@sntech.de>, Quentin Schulz <quentin.schulz@free-electrons.com>, Damian Kos <dkos@cadence.com>, "Piotr Sroka" <piotrs@cadence.com>, <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-rockchip@lists.infradead.org> Subject: [PATCH v6 2/6] drm/dp: fix link probing for devices supporting DP 1.4+ Date: Mon, 8 Oct 2018 22:42:08 +0100 Message-ID: <1539034953-11274-3-git-send-email-dkos@cadence.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1539034953-11274-1-git-send-email-dkos@cadence.com> References: <1539034953-11274-1-git-send-email-dkos@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; 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drm: add support for Cadence MHDP DPI/DP bridge.
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diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 37c01b6076ec..d96ec74a87f5 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -370,10 +370,38 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { u8 values[3]; int err; + unsigned int addr; memset(link, 0, sizeof(*link)); - err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); + /* + * DP 1.4 introduced a DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT bit in + * DP_TRAINING_AUX_RD_INTERVAL register. If set, DPCD registers from + * DP_DPCD_REV to DP_ADAPTER_CAP should be retrieved starting from + * DP_DPCD_REV_EXTENDED. All registers are copied except DP_DPCD_REV, + * DP_MAX_LINK_RATE and DP_DOWNSTREAMPORT_PRESENT which represent the + * "true capabilities" of DPRX device. + * + * Original DP_DPCD_REV, DP_MAX_LINK_RATE and DP_DOWNSTREAMPORT_PRESENT + * might falsely return lower capabilities to "avoid interoperability + * issues with some of the existing DP Source devices that malfunction + * when they discover the higher capabilities within those three + * registers.". + * + * Before DP 1.4, DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT bit was reserved + * and read 0 so it's safe to check against it even if DP revision is + * <1.4 + */ + err = drm_dp_dpcd_readb(aux, DP_TRAINING_AUX_RD_INTERVAL, values); + if (err < 0) + return err; + + if (values[0] & DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) + addr = DP_DP13_DPCD_REV; + else + addr = DP_DPCD_REV; + + err = drm_dp_dpcd_read(aux, addr, values, sizeof(values)); if (err < 0) return err;