From patchwork Tue Oct 9 04:27:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10631893 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 214521867 for ; Tue, 9 Oct 2018 04:29:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12DA029A4D for ; Tue, 9 Oct 2018 04:29:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06F5C29A5C; Tue, 9 Oct 2018 04:29:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8650A29A4D for ; Tue, 9 Oct 2018 04:29:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EFEC6E1B5; Tue, 9 Oct 2018 04:28:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id A7C526E1B5; Tue, 9 Oct 2018 04:28:28 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5DB7360C64; Tue, 9 Oct 2018 04:28:21 +0000 (UTC) Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D4BFB60C82; Tue, 9 Oct 2018 04:28:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D4BFB60C82 From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 21/25] drm/msm/dpu: merge RM reservation helpers Date: Mon, 8 Oct 2018 21:27:38 -0700 Message-Id: <1539059262-8326-22-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539059262-8326-1-git-send-email-jsanka@codeaurora.org> References: <1539059262-8326-1-git-send-email-jsanka@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com, seanpaul@chromium.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP We cleaned up RM reserve api's enough to get rid of most of its unwanted checks and release handlers. To improve further the readability of the function, merging down the individual HW type allocators into one function. Signed-off-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 73 +++++++++++----------------------- 1 file changed, 24 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f794d13..5304597 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -22,15 +22,6 @@ #include "dpu_trace.h" /** - * struct dpu_rm_requirements - Reservation requirements parameter bundle - * @hw_res: Hardware resources required as reported by the encoders - */ -struct dpu_rm_requirements { - struct dpu_encoder_hw_resources hw_res; -}; - - -/** * struct dpu_rm_hw_blk - hardware block tracking list member * @list: List head for list of all hardware blocks tracking items * @in_use: True, if the hw block is assigned to a display pipeline. @@ -427,41 +418,6 @@ static int _dpu_rm_reserve_intfs( return 0; } -static int _dpu_rm_make_reservation( - struct dpu_rm *rm, - struct dpu_crtc_state *dpu_cstate, - struct dpu_rm_requirements *reqs) -{ - int ret; - - ret = _dpu_rm_reserve_lms(rm, dpu_cstate); - if (ret) { - DPU_ERROR("unable to find appropriate mixers\n"); - return ret; - } - - ret = _dpu_rm_reserve_ctls(rm, dpu_cstate); - if (ret) { - DPU_ERROR("unable to find appropriate CTL\n"); - return ret; - } - - ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &reqs->hw_res); - if (ret) { - DPU_ERROR("unable to find appropriate INTF\n"); - return ret; - } - - return ret; -} - -static void _dpu_rm_populate_requirements( - struct drm_encoder *enc, - struct dpu_rm_requirements *reqs) -{ - dpu_encoder_get_hw_resources(enc, &reqs->hw_res); -} - static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type, int id) { @@ -535,7 +491,7 @@ int dpu_rm_reserve( struct drm_encoder *enc, struct drm_crtc_state *crtc_state) { - struct dpu_rm_requirements reqs; + struct dpu_encoder_hw_resources hw_res; struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state); int ret; @@ -548,14 +504,33 @@ int dpu_rm_reserve( mutex_lock(&rm->rm_lock); - _dpu_rm_populate_requirements(enc, &reqs); + dpu_encoder_get_hw_resources(enc, &hw_res); - ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs); + ret = _dpu_rm_reserve_lms(rm, dpu_cstate); if (ret) { - DPU_ERROR("failed to reserve hw resources: %d\n", ret); - _dpu_rm_release_reservation(rm, dpu_cstate); + DPU_ERROR("unable to find appropriate mixers\n"); + goto cleanup_on_fail; } + ret = _dpu_rm_reserve_ctls(rm, dpu_cstate); + if (ret) { + DPU_ERROR("unable to find appropriate CTL\n"); + goto cleanup_on_fail; + } + + ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res); + if (ret) { + DPU_ERROR("unable to find appropriate INTF\n"); + goto cleanup_on_fail; + } + + mutex_unlock(&rm->rm_lock); + + return ret; + +cleanup_on_fail: + _dpu_rm_release_reservation(rm, dpu_cstate); + mutex_unlock(&rm->rm_lock); return ret;