From patchwork Wed Nov 7 08:27:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 10672007 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6F9015A6 for ; Wed, 7 Nov 2018 08:28:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92FC12B2E5 for ; Wed, 7 Nov 2018 08:28:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 864252B484; Wed, 7 Nov 2018 08:28:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F00782B2E5 for ; Wed, 7 Nov 2018 08:28:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C77986E4FE; Wed, 7 Nov 2018 08:28:07 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by gabe.freedesktop.org (Postfix) with ESMTPS id D482C6E47A for ; Wed, 7 Nov 2018 08:27:40 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA78RbTg097579; Wed, 7 Nov 2018 02:27:37 -0600 Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA78Rb2x085746 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 Nov 2018 02:27:37 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 7 Nov 2018 02:27:37 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 7 Nov 2018 02:27:37 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA78RQZq032207; Wed, 7 Nov 2018 02:27:35 -0600 From: Jyri Sarha To: Subject: [PATCH v3 4/8] drm/tidss: Add dispc7 for DSS7 support Date: Wed, 7 Nov 2018 10:27:21 +0200 Message-ID: <1541579245-10715-5-git-send-email-jsarha@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541579245-10715-1-git-send-email-jsarha@ti.com> References: <1541579245-10715-1-git-send-email-jsarha@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.ujfalusi@ti.com, tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, subhajit_paul@ti.com, jjhiblot@ti.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for DSS7 to tidss driver. The DSS7 is a new DSS version found Texas Instruments Keystone AM65x SoC. DSS7 has many similarities to DSS6, but it is different enough to warrant a separate backend driver to keep the code simpler. The DSS7 on AM65x SoC has two video ports and two video pipeline (planes). Only one of the them - called VID - supports scaling, the other is called a VIDL (video lite pipeline). In addition to traditional MIPI DPI output AM65x supports OpenLDI video output. Signed-off-by: Jyri Sarha Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/Kconfig | 16 + drivers/gpu/drm/tidss/Makefile | 7 +- drivers/gpu/drm/tidss/tidss_dispc.h | 1 + drivers/gpu/drm/tidss/tidss_dispc7.c | 2232 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc7.h | 203 +++ drivers/gpu/drm/tidss/tidss_drv.c | 12 + drivers/gpu/drm/tidss/tidss_scale_coefs.c | 185 +++ drivers/gpu/drm/tidss/tidss_scale_coefs.h | 22 + 8 files changed, 2676 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/tidss/tidss_dispc7.c create mode 100644 drivers/gpu/drm/tidss/tidss_dispc7.h create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.c create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.h diff --git a/drivers/gpu/drm/tidss/Kconfig b/drivers/gpu/drm/tidss/Kconfig index 8a8245b..b3e4547 100644 --- a/drivers/gpu/drm/tidss/Kconfig +++ b/drivers/gpu/drm/tidss/Kconfig @@ -12,3 +12,19 @@ config DRM_TIDSS time of writing this these DSSs are found on 66AK2Gx and AM6x SoCs. Set this to Y or M to add display support for TI Keystone family platforms. + +if DRM_TIDSS + +config DRM_TIDSS_DSS6 + bool "DSS6 support" + default y + help + Support for DSS6 IP on K2G SoC + +config DRM_TIDSS_DSS7 + bool "DSS7 support" + default y + help + Support for DSS7 IP on AM6 SoC + +endif diff --git a/drivers/gpu/drm/tidss/Makefile b/drivers/gpu/drm/tidss/Makefile index 6b8b4d4..dd4ec52 100644 --- a/drivers/gpu/drm/tidss/Makefile +++ b/drivers/gpu/drm/tidss/Makefile @@ -1,11 +1,14 @@ # SPDX-License-Identifier: GPL-2.0 tidss-y := tidss_crtc.o \ - tidss_dispc6.o \ tidss_drv.o \ tidss_encoder.o \ tidss_irq.o \ tidss_kms.o \ - tidss_plane.o + tidss_plane.o \ + tidss_scale_coefs.o + +tidss-$(CONFIG_DRM_TIDSS_DSS6) += tidss_dispc6.o +tidss-$(CONFIG_DRM_TIDSS_DSS7) += tidss_dispc7.o obj-$(CONFIG_DRM_TIDSS) += tidss.o diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 18c87d5..3ada991 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -136,5 +136,6 @@ struct tidss_dispc_ops { }; int dispc6_init(struct tidss_device *tidss); +int dispc7_init(struct tidss_device *tidss); #endif diff --git a/drivers/gpu/drm/tidss/tidss_dispc7.c b/drivers/gpu/drm/tidss/tidss_dispc7.c new file mode 100644 index 0000000..d97bca1 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_dispc7.c @@ -0,0 +1,2232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "tidss_drv.h" +#include "tidss_crtc.h" +#include "tidss_plane.h" +#include "tidss_encoder.h" + +#include "tidss_dispc.h" +#include "tidss_scale_coefs.h" +#include "tidss_dispc7.h" + +static const struct dispc7_features dispc7_am6_feats = { + .min_pclk = 1000, + .max_pclk = 200000000, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DISPC7_VP_OLDI, DISPC7_VP_DPI }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, +}; + +static const struct of_device_id dispc7_of_table[] = { + { .compatible = "ti,am6-dss", .data = &dispc7_am6_feats }, + { } +}; + +/* + * TRM gives bitfields as start:end, where start is the higher bit + * number. For example 7:0 + */ + +#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) +#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) +#define FLD_MOD(orig, val, start, end) \ + (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) + +#define REG_GET(dispc, idx, start, end) \ + FLD_GET(dispc7_read(dispc, idx), start, end) + +#define REG_FLD_MOD(dispc, idx, val, start, end) \ + dispc7_write(dispc, idx, FLD_MOD(dispc7_read(dispc, idx), val, start, end)) + +#define VID_REG_GET(dispc, hw_plane, idx, start, end) \ + FLD_GET(dispc7_vid_read(dispc, hw_plane, idx), start, end) + +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ + dispc7_vid_write(dispc, hw_plane, idx, FLD_MOD(dispc7_vid_read(dispc, hw_plane, idx), val, start, end)) + +#define VP_REG_GET(dispc, vp, idx, start, end) \ + FLD_GET(dispc7_vp_read(dispc, vp, idx), start, end) + +#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ + dispc7_vp_write(dispc, vp, idx, FLD_MOD(dispc7_vp_read(dispc, vp, idx), val, start, end)) + +#define OVR_REG_GET(dispc, ovr, idx, start, end) \ + FLD_GET(dispc7_ovr_read(dispc, ovr, idx), start, end) + +#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ + dispc7_ovr_write(dispc, ovr, idx, FLD_MOD(dispc7_ovr_read(dispc, ovr, idx), val, start, end)) + +#define DISPC7_GAMMA_TABLE_SIZE 256 + +struct dss_vp_data { + u32 gamma_table[DISPC7_GAMMA_TABLE_SIZE]; +}; + +struct dss_plane_data { + u32 zorder; + u32 hw_videoport; +}; + +struct dispc_device { + struct tidss_device *tidss; + struct device *dev; + + void __iomem *base_common; + void __iomem *base_vid[DISPC7_MAX_PLANES]; + void __iomem *base_ovr[DISPC7_MAX_PORTS]; + void __iomem *base_vp[DISPC7_MAX_PORTS]; + + struct regmap *syscon; + + struct clk *vp_clk[DISPC7_MAX_PORTS]; + + const struct dispc7_features *feat; + + struct clk *fclk; + + bool is_enabled; + + struct dss_vp_data vp_data[DISPC7_MAX_PORTS]; + + struct dss_plane_data plane_data[DISPC7_MAX_PLANES]; +}; + + +static void dispc7_write(struct dispc_device *dispc, u16 reg, u32 val) +{ + iowrite32(val, dispc->base_common + reg); +} + +static u32 dispc7_read(struct dispc_device *dispc, u16 reg) +{ + return ioread32(dispc->base_common + reg); +} + +static void dispc7_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) +{ + void __iomem *base = dispc->base_vid[hw_plane]; + + iowrite32(val, base + reg); +} + +static u32 dispc7_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) +{ + void __iomem *base = dispc->base_vid[hw_plane]; + + return ioread32(base + reg); +} + +static void dispc7_ovr_write(struct dispc_device *dispc, u32 hw_videoport, u16 reg, u32 val) +{ + void __iomem *base = dispc->base_ovr[hw_videoport]; + + iowrite32(val, base + reg); +} + +static u32 dispc7_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) +{ + void __iomem *base = dispc->base_ovr[hw_videoport]; + + return ioread32(base + reg); +} + +static void dispc7_vp_write(struct dispc_device *dispc, u32 hw_videoport, u16 reg, u32 val) +{ + void __iomem *base = dispc->base_vp[hw_videoport]; + + iowrite32(val, base + reg); +} + +static u32 dispc7_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) +{ + void __iomem *base = dispc->base_vp[hw_videoport]; + + return ioread32(base + reg); +} + + +static int dispc7_runtime_get(struct dispc_device *dispc) +{ + int r; + + dev_dbg(dispc->dev, "%s\n", __func__); + + r = pm_runtime_get_sync(dispc->dev); + WARN_ON(r < 0); + return r < 0 ? r : 0; +} + +static void dispc7_runtime_put(struct dispc_device *dispc) +{ + int r; + + dev_dbg(dispc->dev, "%s\n", __func__); + + r = pm_runtime_put_sync(dispc->dev); + WARN_ON(r < 0); +} + +static u64 dispc7_vp_irq_from_raw(u32 stat, u32 hw_videoport) +{ + u64 vp_stat = 0; + + if (stat & BIT(0)) + vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport); + if (stat & BIT(1)) + vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport); + if (stat & BIT(2)) + vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport); + if (stat & BIT(4)) + vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport); + + return vp_stat; +} + +static u32 dispc7_vp_irq_to_raw(u64 vpstat, u32 hw_videoport) +{ + u32 stat = 0; + + if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport)) + stat |= BIT(0); + if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport)) + stat |= BIT(1); + if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport)) + stat |= BIT(2); + if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport)) + stat |= BIT(4); + + return stat; +} + +static u64 dispc7_vid_irq_from_raw(u32 stat, u32 hw_plane) +{ + u64 vid_stat = 0; + + if (stat & BIT(0)) + vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane); + + return vid_stat; +} + +static u32 dispc7_vid_irq_to_raw(u64 vidstat, u32 hw_plane) +{ + u32 stat = 0; + + if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane)) + stat |= BIT(0); + + return stat; +} + +static u64 dispc7_vp_read_irqstatus(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc7_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); + + return dispc7_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc7_vp_write_irqstatus(struct dispc_device *dispc, + u32 hw_videoport, u64 vpstat) +{ + u32 stat = dispc7_vp_irq_to_raw(vpstat, hw_videoport); + + dispc7_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); +} + +static u64 dispc7_vid_read_irqstatus(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc7_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); + + return dispc7_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc7_vid_write_irqstatus(struct dispc_device *dispc, + u32 hw_plane, u64 vidstat) +{ + u32 stat = dispc7_vid_irq_to_raw(vidstat, hw_plane); + + dispc7_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); +} + +static u64 dispc7_vp_read_irqenable(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc7_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); + + return dispc7_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc7_vp_write_irqenable(struct dispc_device *dispc, + u32 hw_videoport, u64 vpstat) +{ + u32 stat = dispc7_vp_irq_to_raw(vpstat, hw_videoport); + + dispc7_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); +} + + +static u64 dispc7_vid_read_irqenable(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc7_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); + + return dispc7_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc7_vid_write_irqenable(struct dispc_device *dispc, + u32 hw_plane, u64 vidstat) +{ + u32 stat = dispc7_vid_irq_to_raw(vidstat, hw_plane); + + dispc7_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); +} + +static void dispc7_clear_irqstatus(struct dispc_device *dispc, u64 clearmask) +{ + unsigned int i; + u32 top_clear = 0; + + for (i = 0; i < dispc->feat->num_vps; ++i) { + if (clearmask & DSS_IRQ_VP_MASK(i)) { + dispc7_vp_write_irqstatus(dispc, i, clearmask); + top_clear |= BIT(i); + } + } + for (i = 0; i < dispc->feat->num_planes; ++i) { + if (clearmask & DSS_IRQ_PLANE_MASK(i)) { + dispc7_vid_write_irqstatus(dispc, i, clearmask); + top_clear |= BIT(4 + i); + } + } + dispc7_write(dispc, DISPC_IRQSTATUS, top_clear); + + /* Flush posted writes */ + dispc7_read(dispc, DISPC_IRQSTATUS); +} + +static u64 dispc7_read_and_clear_irqstatus(struct dispc_device *dispc) +{ + u64 status = 0; + unsigned int i; + + for (i = 0; i < dispc->feat->num_vps; ++i) + status |= dispc7_vp_read_irqstatus(dispc, i); + + for (i = 0; i < dispc->feat->num_planes; ++i) + status |= dispc7_vid_read_irqstatus(dispc, i); + + dispc7_clear_irqstatus(dispc, status); + + return status; +} + +static u64 dispc7_read_irqenable(struct dispc_device *dispc) +{ + u64 enable = 0; + unsigned int i; + + for (i = 0; i < dispc->feat->num_vps; ++i) + enable |= dispc7_vp_read_irqenable(dispc, i); + + for (i = 0; i < dispc->feat->num_planes; ++i) + enable |= dispc7_vid_read_irqenable(dispc, i); + + return enable; +} + +static void dispc7_write_irqenable(struct dispc_device *dispc, u64 mask) +{ + unsigned int i; + u32 main_enable = 0, main_disable = 0; + u64 old_mask; + + old_mask = dispc7_read_irqenable(dispc); + + /* clear the irqstatus for newly enabled irqs */ + dispc7_clear_irqstatus(dispc, (old_mask ^ mask) & mask); + + for (i = 0; i < dispc->feat->num_vps; ++i) { + dispc7_vp_write_irqenable(dispc, i, mask); + if (mask & DSS_IRQ_VP_MASK(i)) + main_enable |= BIT(i); /* VP IRQ */ + else + main_disable |= BIT(i); /* VP IRQ */ + } + + for (i = 0; i < dispc->feat->num_planes; ++i) { + dispc7_vid_write_irqenable(dispc, i, mask); + if (mask & DSS_IRQ_PLANE_MASK(i)) + main_enable |= BIT(i + 4); /* VID IRQ */ + else + main_disable |= BIT(i + 4); /* VID IRQ */ + } + + if (main_enable) + dispc7_write(dispc, DISPC_IRQENABLE_SET, main_enable); + + if (main_disable) + dispc7_write(dispc, DISPC_IRQENABLE_CLR, main_disable); + + /* Flush posted writes */ + dispc7_read(dispc, DISPC_IRQENABLE_SET); +} + +enum dispc7_oldi_mode { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; + +struct dispc7_bus_format { + u32 bus_fmt; + u32 data_width; + enum dispc7_vp_bus_type bus_type; + enum dispc7_oldi_mode oldi_mode; +}; + +static const struct dispc7_bus_format dispc7_bus_formats[] = { + { MEDIA_BUS_FMT_RGB444_1X12, 12, DISPC7_VP_DPI, 0 }, + { MEDIA_BUS_FMT_RGB565_1X16, 16, DISPC7_VP_DPI, 0 }, + { MEDIA_BUS_FMT_RGB666_1X18, 18, DISPC7_VP_DPI, 0 }, + { MEDIA_BUS_FMT_RGB888_1X24, 24, DISPC7_VP_DPI, 0 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, DISPC7_VP_OLDI, SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, DISPC7_VP_OLDI, SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, DISPC7_VP_OLDI, JEIDA_24 }, +}; + +static const +struct dispc7_bus_format *dispc7_vp_find_bus_fmt(struct dispc_device *dispc, + u32 hw_videoport, + u32 bus_fmt, u32 bus_flags) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc7_bus_formats); ++i) { + if (dispc7_bus_formats[i].bus_fmt == bus_fmt) + return &dispc7_bus_formats[i]; + } + + return NULL; +} + +static void dispc7_oldi_tx_power(struct dispc_device *dispc, bool power) +{ + u32 val = power ? 0 : CTRLMMR0P1_OLDI_PWRDN_TX; + + if (WARN_ON(!dispc->syscon)) + return; + + regmap_update_bits(dispc->syscon, CTRLMMR0P1_OLDI_DAT0_IO_CTRL, + CTRLMMR0P1_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->syscon, CTRLMMR0P1_OLDI_DAT1_IO_CTRL, + CTRLMMR0P1_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->syscon, CTRLMMR0P1_OLDI_DAT2_IO_CTRL, + CTRLMMR0P1_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->syscon, CTRLMMR0P1_OLDI_DAT3_IO_CTRL, + CTRLMMR0P1_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->syscon, CTRLMMR0P1_OLDI_CLK_IO_CTRL, + CTRLMMR0P1_OLDI_PWRDN_TX, val); +} + +static void dispc7_set_num_datalines(struct dispc_device *dispc, + u32 hw_videoport, int num_lines) +{ + int v; + + switch (num_lines) { + case 12: + v = 0; break; + case 16: + v = 1; break; + case 18: + v = 2; break; + case 24: + v = 3; break; + case 30: + v = 4; break; + case 36: + v = 5; break; + default: + WARN_ON(1); + v = 3; + } + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); +} + +static void dispc7_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, + const struct dispc7_bus_format *fmt) +{ + u32 oldi_cfg = 0; + u32 oldi_reset_bit = BIT(5 + hw_videoport); + int count = 0; + + /* + * On am6 DUALMODESYNC, MASTERSLAVE, MODE, and SRC are set + * statically to 0. + */ + + if (fmt->data_width == 24) + oldi_cfg |= BIT(8); /* MSB */ + else if (fmt->data_width != 18) + dev_warn(dispc->dev, "%s: %d port width not supported\n", + __func__, fmt->data_width); + + oldi_cfg |= BIT(7); /* DEPOL */ + + oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode, 3, 1); + + oldi_cfg |= BIT(12); /* SOFTRST */ + + oldi_cfg |= BIT(0); /* ENABLE */ + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + + while (!(oldi_reset_bit & dispc7_read(dispc, DSS_SYSSTATUS)) && + count < 10000) + count++; + + if (!(oldi_reset_bit & dispc7_read(dispc, DSS_SYSSTATUS))) + dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", + __func__); +} + +static void dispc7_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + const struct dispc7_bus_format *fmt; + + fmt = dispc7_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + + if (WARN_ON(!fmt)) + return; + + if (WARN_ON(dispc->feat->vp_bus_type[hw_videoport] != fmt->bus_type)) + return; + + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC7_VP_OLDI) { + dispc7_oldi_tx_power(dispc, true); + + dispc7_enable_oldi(dispc, hw_videoport, fmt); + } +} + +static void dispc7_vp_enable(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct drm_display_mode *mode = &state->adjusted_mode; + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + bool align, onoff, rf, ieo, ipc, ihs, ivs; + const struct dispc7_bus_format *fmt; + u32 hsw, hfp, hbp, vsw, vfp, vbp; + + fmt = dispc7_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + + if (WARN_ON(!fmt)) + return; + + dispc7_set_num_datalines(dispc, hw_videoport, fmt->data_width); + + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsw = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, + FLD_VAL(hsw - 1, 7, 0) | + FLD_VAL(hfp - 1, 19, 8) | + FLD_VAL(hbp - 1, 31, 20)); + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, + FLD_VAL(vsw - 1, 7, 0) | + FLD_VAL(vfp, 19, 8) | + FLD_VAL(vbp, 31, 20)); + + ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + + ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); + + ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE); + + /* always use the 'rf' setting */ + onoff = true; + + rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_POSEDGE); + + /* always use aligned syncs */ + align = true; + + /* always use DE_HIGH for OLDI */ + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC7_VP_OLDI) + ieo = false; + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, + FLD_VAL(align, 18, 18) | + FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(ieo, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(ihs, 13, 13) | + FLD_VAL(ivs, 12, 12)); + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, + FLD_VAL(mode->hdisplay - 1, 11, 0) | + FLD_VAL(mode->vdisplay - 1, 27, 16)); + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); +} + +static void dispc7_vp_disable(struct dispc_device *dispc, u32 hw_videoport) +{ + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); +} + +static void dispc7_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) +{ + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC7_VP_OLDI) { + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); + + dispc7_oldi_tx_power(dispc, false); + } +} + +static bool dispc7_vp_go_busy(struct dispc_device *dispc, + u32 hw_videoport) +{ + return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); +} + +static void dispc7_vp_go(struct dispc_device *dispc, u32 hw_videoport) +{ + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); +} + +enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; + +static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) +{ + u16 c12; + + c12 = c8 << 4; + + switch (mode) { + case C8_TO_C12_REPLICATE: + /* Copy c8 4 MSB to 4 LSB for full scale c12 */ + c12 |= c8 >> 4; + break; + case C8_TO_C12_MAX: + c12 |= 0xF; + break; + default: + case C8_TO_C12_MIN: + break; + }; + + return c12; +} + +static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) +{ + u8 a, r, g, b; + u64 v; + + a = (argb8888 >> 24) & 0xff; + r = (argb8888 >> 16) & 0xff; + g = (argb8888 >> 8) & 0xff; + b = (argb8888 >> 0) & 0xff; + + v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | + ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m); + + return v; +} + +static void dispc7_vp_set_default_color(struct dispc_device *dispc, + u32 hw_videoport, u32 default_color) +{ + u64 v; + + v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE); + + dispc7_ovr_write(dispc, hw_videoport, + DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff); + dispc7_ovr_write(dispc, hw_videoport, + DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); +} + +static enum drm_mode_status dispc7_vp_mode_valid(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_display_mode *mode) +{ + u32 hsw, hfp, hbp, vsw, vfp, vbp; + + if (mode->clock * 1000 < dispc->feat->min_pclk) + return MODE_CLOCK_LOW; + + if (mode->clock * 1000 > dispc->feat->max_pclk) + return MODE_CLOCK_HIGH; + + if (mode->hdisplay > 4096) + return MODE_BAD; + + if (mode->vdisplay > 4096) + return MODE_BAD; + + /* TODO: add interlace support */ + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_NO_INTERLACE; + + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsw = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + if (hsw < 1 || hsw > 256 || + hfp < 1 || hfp > 4096 || + hbp < 1 || hbp > 4096) + return MODE_BAD_HVALUE; + + if (vsw < 1 || vsw > 256 || + vfp < 0 || vfp > 4095 || + vbp < 0 || vbp > 4095) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + +static int dispc7_vp_check(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct drm_display_mode *mode = &state->adjusted_mode; + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + const struct dispc7_bus_format *fmt; + enum drm_mode_status ok; + + ok = dispc7_vp_mode_valid(dispc, hw_videoport, mode); + if (ok != MODE_OK) { + dev_dbg(dispc->dev, "%s: bad mode: %ux%u pclk %u kHz\n", + __func__, mode->hdisplay, mode->vdisplay, mode->clock); + return -EINVAL; + } + + fmt = dispc7_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + if (!fmt) { + dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", + __func__, tstate->bus_format); + return -EINVAL; + } + + if (dispc->feat->vp_bus_type[hw_videoport] != fmt->bus_type) { + dev_dbg(dispc->dev, "%s: %s is not %s-port\n", + __func__, dispc->feat->vp_name[hw_videoport], + fmt->bus_type == DISPC7_VP_OLDI ? "OLDI" : "DPI"); + return -EINVAL; + } + + return 0; +} + +static int dispc7_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) +{ + int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); + + if (ret) + dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, + ret); + + return ret; +} + +static void dispc7_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) +{ + clk_disable_unprepare(dispc->vp_clk[hw_videoport]); +} + +/* + * Calculate the percentage difference between the requested pixel clock rate + * and the effective rate resulting from calculating the clock divider value. + */ +static unsigned int dispc7_pclk_diff(unsigned long rate, + unsigned long real_rate) +{ + int r = rate / 100, rr = real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +static int dispc7_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, + unsigned long rate) +{ + int r; + unsigned long new_rate; + + r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); + if (r) { + dev_err(dispc->dev, "Failed to set vp%d clk rate to %lu\n", + hw_videoport, rate); + return r; + } + + new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); + + if (dispc7_pclk_diff(rate, new_rate) > 5) + dev_warn(dispc->dev, + "Clock rate %lu differs over 5%% from requsted %lu\n", + new_rate, rate); + + dev_dbg(dispc->dev, "New VP%d rate %lu Hz (requested %lu Hz)\n", + hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); + + return 0; +} + +/* OVR */ +static void dispc7_ovr_set_plane(struct dispc_device *dispc, + u32 hw_plane, u32 hw_videoport, + u32 x, u32 y, u32 zpos) +{ + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + hw_plane, 4, 1); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + x, 17, 6); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + y, 30, 19); +} + +static void dispc7_ovr_enable_plane(struct dispc_device *dispc, + u32 hw_videoport, u32 zpos, bool enable) +{ + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + !!enable, 0, 0); +} + +/* CSC */ +enum csc_ctm { + CSC_RR, CSC_RG, CSC_RB, + CSC_GR, CSC_GG, CSC_GB, + CSC_BR, CSC_BG, CSC_BB, +}; + +enum csc_yuv2rgb { + CSC_RY, CSC_RCb, CSC_RCr, + CSC_GY, CSC_GCb, CSC_GCr, + CSC_BY, CSC_BCb, CSC_BCr, +}; + +enum csc_rgb2yuv { + CSC_YR, CSC_YG, CSC_YB, + CSC_CbR, CSC_CbG, CSC_CbB, + CSC_CrR, CSC_CrG, CSC_CrB, +}; + +struct dispc7_csc_coef { + void (*to_regval)(const struct dispc7_csc_coef *csc, u32 *regval); + int m[9]; + int preoffset[3]; + int postoffset[3]; + enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping; + const char *name; +}; + +#define DISPC7_CSC_REGVAL_LEN 8 + +static void dispc7_csc_offset_regval(const struct dispc7_csc_coef *csc, + u32 *regval) +{ +#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) + regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); + regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); + regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); +#undef OVAL +} + +#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +static void dispc7_csc_yuv2rgb_regval(const struct dispc7_csc_coef *csc, + u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCr]); + regval[1] = CVAL(csc->m[CSC_RCb], csc->m[CSC_GY]); + regval[2] = CVAL(csc->m[CSC_GCr], csc->m[CSC_GCb]); + regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCr]); + regval[4] = CVAL(csc->m[CSC_BCb], 0); + + dispc7_csc_offset_regval(csc, regval); +} + +static void __maybe_unused dispc7_csc_rgb2yuv_regval(const struct dispc7_csc_coef *csc, + u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); + regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CrR]); + regval[2] = CVAL(csc->m[CSC_CrG], csc->m[CSC_CrB]); + regval[3] = CVAL(csc->m[CSC_CbR], csc->m[CSC_CbG]); + regval[4] = CVAL(csc->m[CSC_CbB], 0); + + dispc7_csc_offset_regval(csc, regval); +} + +static void dispc7_csc_cpr_regval(const struct dispc7_csc_coef *csc, + u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); + regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); + regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); + regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); + regval[4] = CVAL(csc->m[CSC_BB], 0); + + dispc7_csc_offset_regval(csc, regval); +} +#undef CVAL + + +static void dispc7_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, + const struct dispc7_csc_coef *csc) +{ + static const u16 dispc_vid_csc_coef_reg[DISPC7_CSC_REGVAL_LEN] = { + DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), + DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), + DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), + DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7, + }; + u32 regval[DISPC7_CSC_REGVAL_LEN]; + unsigned int i; + + csc->to_regval(csc, regval); + + for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++) + dispc7_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], + regval[i]); +} + +/* YUV -> RGB, ITU-R BT.601, full range */ +const static struct dispc7_csc_coef csc_yuv2rgb_bt601_full = { + dispc7_csc_yuv2rgb_regval, + { 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/ + 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/ + 256, 452, 0, }, /* by, bcb, bcr |1.000 1.772 0.000|*/ + { 0, -2048, -2048, }, /* full range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.601 Full", +}; + +/* YUV -> RGB, ITU-R BT.601, limited range */ +const static struct dispc7_csc_coef csc_yuv2rgb_bt601_lim = { + dispc7_csc_yuv2rgb_regval, + { 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/ + 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/ + 298, 516, 0, }, /* by, bcb, bcr |1.164 2.017 0.000|*/ + { -256, -2048, -2048, }, /* limited range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.601 Limited", +}; + +/* YUV -> RGB, ITU-R BT.709, full range */ +const static struct dispc7_csc_coef csc_yuv2rgb_bt709_full = { + dispc7_csc_yuv2rgb_regval, + { 256, 0, 402, /* ry, rcb, rcr |1.000 0.000 1.570|*/ + 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/ + 256, 475, 0, }, /* by, bcb, bcr |1.000 1.856 0.000|*/ + { 0, -2048, -2048, }, /* full range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.709 Full", +}; + +/* YUV -> RGB, ITU-R BT.709, limited range */ +const static struct dispc7_csc_coef csc_yuv2rgb_bt709_lim = { + dispc7_csc_yuv2rgb_regval, + { 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/ + 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/ + 298, 541, 0, }, /* by, bcb, bcr |1.164 2.112 0.000|*/ + { -256, -2048, -2048, }, /* limited range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.709 Limited", +}; + +static const struct { + enum drm_color_encoding encoding; + enum drm_color_range range; + const struct dispc7_csc_coef *csc; +} dispc7_csc_table[] = { + { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE, + &csc_yuv2rgb_bt601_full, }, + { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE, + &csc_yuv2rgb_bt601_lim, }, + { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_FULL_RANGE, + &csc_yuv2rgb_bt709_full, }, + { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + &csc_yuv2rgb_bt709_lim, }, +}; + +static const +struct dispc7_csc_coef *dispc7_find_csc(enum drm_color_encoding encoding, + enum drm_color_range range) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc7_csc_table); i++) { + if (dispc7_csc_table[i].encoding == encoding && + dispc7_csc_table[i].range == range) { + return dispc7_csc_table[i].csc; + } + } + return NULL; +} + +static void dispc7_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state) +{ + const static struct dispc7_csc_coef *coef; + + coef = dispc7_find_csc(state->color_encoding, state->color_range); + if (!coef) { + dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", + __func__, state->color_encoding, state->color_range); + return; + } + + dispc7_vid_write_csc(dispc, hw_plane, coef); +} + +static void dispc7_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, + bool enable) +{ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); +} + +/* SCALER */ + +static u32 dispc7_calc_fir_inc(u32 in, u32 out) +{ + return (u32)div_u64(0x200000ull * in, out); +} + +enum dispc7_vid_fir_coef_set { + DISPC7_VID_FIR_COEF_HORIZ, + DISPC7_VID_FIR_COEF_HORIZ_UV, + DISPC7_VID_FIR_COEF_VERT, + DISPC7_VID_FIR_COEF_VERT_UV, +}; + +static void dispc7_vid_write_fir_coefs(struct dispc_device *dispc, + u32 hw_plane, + enum dispc7_vid_fir_coef_set coef_set, + const struct tidss_scale_coefs *coefs) +{ + static const u16 c0_regs[] = { + [DISPC7_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H0, + [DISPC7_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H0_C, + [DISPC7_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V0, + [DISPC7_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V0_C, + }; + + static const u16 c12_regs[] = { + [DISPC7_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H12, + [DISPC7_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H12_C, + [DISPC7_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V12, + [DISPC7_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V12_C, + }; + + const u16 c0_base = c0_regs[coef_set]; + const u16 c12_base = c12_regs[coef_set]; + int phase; + + if (!coefs) { + dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); + return; + } + + for (phase = 0; phase <= 8; ++phase) { + u16 reg = c0_base + phase * 4; + u16 c0 = coefs->c0[phase]; + + dispc7_vid_write(dispc, hw_plane, reg, c0); + } + + for (phase = 0; phase <= 15; ++phase) { + u16 reg = c12_base + phase * 4; + s16 c1, c2; + u32 c12; + + c1 = coefs->c1[phase]; + c2 = coefs->c2[phase]; + c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + + dispc7_vid_write(dispc, hw_plane, reg, c12); + } +} + +static bool dispc7_fourcc_is_yuv(u32 fourcc) +{ + switch (fourcc) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_NV12: + return true; + default: + return false; + } +} + +struct dispc7_scaling_params { + int xinc, yinc; + u32 in_w, in_h, in_w_uv, in_h_uv; + u32 fir_xinc, fir_yinc, fir_xinc_uv, fir_yinc_uv; + bool scale_x, scale_y; + const struct tidss_scale_coefs *xcoef, *ycoef, *xcoef_uv, *ycoef_uv; + bool five_taps; +}; + +static int dispc7_vid_calc_scaling(struct dispc_device *dispc, + const struct drm_plane_state *state, + struct dispc7_scaling_params *sp, + bool lite_plane) +{ + const struct dispc7_features_scaling *f = &dispc->feat->scaling; + u32 fourcc = state->fb->format->format; + u32 in_width_max_5tap = f->in_width_max_5tap_rgb; + u32 in_width_max_3tap = f->in_width_max_3tap_rgb; + u32 downscale_limit; + u32 in_width_max; + + memset(sp, 0, sizeof(*sp)); + sp->xinc = sp->yinc = 1; + sp->in_w = sp->in_w_uv = state->src_w >> 16; + sp->in_h = sp->in_h_uv = state->src_h >> 16; + + sp->scale_x = sp->in_w != state->crtc_w; + sp->scale_y = sp->in_h != state->crtc_h; + + if (dispc7_fourcc_is_yuv(fourcc)) { + in_width_max_5tap = f->in_width_max_5tap_yuv; + in_width_max_3tap = f->in_width_max_3tap_yuv; + + sp->in_w_uv >>= 1; + sp->scale_x = true; + + if (fourcc == DRM_FORMAT_NV12) { + sp->in_h_uv >>= 1; + sp->scale_y = true; + } + } + + /* Skip the rest if no scaling is used */ + if ((!sp->scale_x && !sp->scale_y) || lite_plane) + return 0; + + if (sp->in_w > in_width_max_5tap) { + sp->five_taps = false; + in_width_max = in_width_max_3tap; + downscale_limit = f->downscale_limit_3tap; + } else { + sp->five_taps = true; + in_width_max = in_width_max_5tap; + downscale_limit = f->downscale_limit_5tap; + } + + if (sp->scale_x) { + sp->fir_xinc = dispc7_calc_fir_inc(sp->in_w, state->crtc_w); + + if (sp->fir_xinc < dispc7_calc_fir_inc(1, f->upscale_limit)) { + dev_dbg(dispc->dev, + "%s: X-scaling factor %u/%u > %u\n", + __func__, state->crtc_w, state->src_w >> 16, + f->upscale_limit); + return -EINVAL; + } + + if (sp->fir_xinc >= dispc7_calc_fir_inc(downscale_limit, 1)) { + sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, + state->crtc_w), + downscale_limit); + + if (sp->xinc > f->xinc_max) { + dev_dbg(dispc->dev, + "%s: X-scaling factor %u/%u < 1/%u\n", + __func__, state->crtc_w, + state->src_w >> 16, + downscale_limit * f->xinc_max); + return -EINVAL; + } + + sp->in_w = (state->src_w >> 16) / sp->xinc; + } + + while (sp->in_w > in_width_max) { + sp->xinc++; + sp->in_w = (state->src_w >> 16) / sp->xinc; + } + + if (sp->xinc > f->xinc_max) { + dev_dbg(dispc->dev, + "%s: Too wide input bufer %u > %u\n", __func__, + state->src_w >> 16, in_width_max * f->xinc_max); + return -EINVAL; + } + + /* + * We need even line length for YUV formats. Decimation + * can lead to odd length, so we need to make it even + * again. + */ + if (dispc7_fourcc_is_yuv(fourcc)) + sp->in_w &= ~1; + + sp->fir_xinc = dispc7_calc_fir_inc(sp->in_w, state->crtc_w); + } + + if (sp->scale_y) { + sp->fir_yinc = dispc7_calc_fir_inc(sp->in_h, state->crtc_h); + + if (sp->fir_yinc < dispc7_calc_fir_inc(1, f->upscale_limit)) { + dev_dbg(dispc->dev, + "%s: Y-scaling factor %u/%u > %u\n", + __func__, state->crtc_h, state->src_h >> 16, + f->upscale_limit); + return -EINVAL; + } + + if (sp->fir_yinc >= dispc7_calc_fir_inc(downscale_limit, 1)) { + sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, + state->crtc_h), + downscale_limit); + + sp->in_h /= sp->yinc; + sp->fir_yinc = dispc7_calc_fir_inc(sp->in_h, + state->crtc_h); + } + } + + dev_dbg(dispc->dev, + "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", + __func__, state->src_w >> 16, state->src_h >> 16, + sp->xinc, sp->yinc, sp->in_w, sp->in_h, + sp->fir_xinc / 0x200000u, + ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, + sp->fir_yinc / 0x200000u, + ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, + sp->five_taps ? 5 : 3, + state->crtc_w, state->crtc_h); + + if (dispc7_fourcc_is_yuv(fourcc)) { + if (sp->scale_x) { + sp->in_w_uv /= sp->xinc; + sp->fir_xinc_uv = dispc7_calc_fir_inc(sp->in_w_uv, + state->crtc_w); + sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, + sp->fir_xinc_uv, + true); + } + if (sp->scale_y) { + sp->in_h_uv /= sp->yinc; + sp->fir_yinc_uv = dispc7_calc_fir_inc(sp->in_h_uv, + state->crtc_h); + sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, + sp->fir_yinc_uv, + sp->five_taps); + } + } + + if (sp->scale_x) + sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, + true); + + if (sp->scale_y) + sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, + sp->five_taps); + + return 0; +} + +static void dispc7_vid_set_scaling(struct dispc_device *dispc, + u32 hw_plane, + struct dispc7_scaling_params *sp, + u32 fourcc) +{ + /* HORIZONTAL RESIZE ENABLE */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->scale_x, 7, 7); + + /* VERTICAL RESIZE ENABLE */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->scale_y, 8, 8); + + /* Skip the rest if no scaling is used */ + if (!sp->scale_x && !sp->scale_y) + return; + + /* VERTICAL 5-TAPS */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->five_taps, 21, 21); + + if (dispc7_fourcc_is_yuv(fourcc)) { + if (sp->scale_x) { + dispc7_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, + sp->fir_xinc_uv); + dispc7_vid_write_fir_coefs(dispc, hw_plane, + DISPC7_VID_FIR_COEF_HORIZ_UV, + sp->xcoef_uv); + } + if (sp->scale_y) { + dispc7_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, + sp->fir_yinc_uv); + dispc7_vid_write_fir_coefs(dispc, hw_plane, + DISPC7_VID_FIR_COEF_VERT_UV, + sp->ycoef_uv); + } + } + + if (sp->scale_x) { + dispc7_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); + dispc7_vid_write_fir_coefs(dispc, hw_plane, + DISPC7_VID_FIR_COEF_HORIZ, + sp->xcoef); + } + + if (sp->scale_y) { + dispc7_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); + dispc7_vid_write_fir_coefs(dispc, hw_plane, + DISPC7_VID_FIR_COEF_VERT, sp->ycoef); + } +} + +/* OTHER */ + +static const struct { + u32 fourcc; + u8 dss_code; +} dispc7_color_formats[] = { + { DRM_FORMAT_ARGB4444, 0x0, }, + { DRM_FORMAT_ABGR4444, 0x1, }, + { DRM_FORMAT_RGBA4444, 0x2, }, + + { DRM_FORMAT_RGB565, 0x3, }, + { DRM_FORMAT_BGR565, 0x4, }, + + { DRM_FORMAT_ARGB1555, 0x5, }, + { DRM_FORMAT_ABGR1555, 0x6, }, + + { DRM_FORMAT_ARGB8888, 0x7, }, + { DRM_FORMAT_ABGR8888, 0x8, }, + { DRM_FORMAT_RGBA8888, 0x9, }, + { DRM_FORMAT_BGRA8888, 0xa, }, + + { DRM_FORMAT_RGB888, 0xb, }, + { DRM_FORMAT_BGR888, 0xc, }, + + { DRM_FORMAT_ARGB2101010, 0xe, }, + { DRM_FORMAT_ABGR2101010, 0xf, }, + { DRM_FORMAT_RGBA1010102, 0x10, }, + { DRM_FORMAT_BGRA1010102, 0x11, }, + + { DRM_FORMAT_XRGB4444, 0x20, }, + { DRM_FORMAT_XBGR4444, 0x21, }, + { DRM_FORMAT_RGBX4444, 0x22, }, + + { DRM_FORMAT_ARGB1555, 0x25, }, + { DRM_FORMAT_ABGR1555, 0x26, }, + + { DRM_FORMAT_XRGB8888, 0x27, }, + { DRM_FORMAT_XBGR8888, 0x28, }, + { DRM_FORMAT_RGBX8888, 0x29, }, + { DRM_FORMAT_BGRX8888, 0x2a, }, + + { DRM_FORMAT_XRGB2101010, 0x2e, }, + { DRM_FORMAT_XBGR2101010, 0x2f, }, + { DRM_FORMAT_RGBX1010102, 0x30, }, + { DRM_FORMAT_BGRX1010102, 0x31, }, + + { DRM_FORMAT_YUYV, 0x3e, }, + { DRM_FORMAT_UYVY, 0x3f, }, + + { DRM_FORMAT_NV12, 0x3d, }, +}; + +static void dispc7_plane_set_pixel_format(struct dispc_device *dispc, + u32 hw_plane, u32 fourcc) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc7_color_formats); ++i) { + if (dispc7_color_formats[i].fourcc == fourcc) { + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + dispc7_color_formats[i].dss_code, + 6, 1); + return; + } + } + + WARN_ON(1); +} + +static s32 pixinc(int pixels, u8 ps) +{ + if (pixels == 1) + return 1; + else if (pixels > 1) + return 1 + (pixels - 1) * ps; + else if (pixels < 0) + return 1 - (-pixels + 1) * ps; + + WARN_ON(1); + return 0; +} + +static +const struct tidss_plane_feat *dispc7_plane_feat(struct dispc_device *dispc, + u32 hw_plane) +{ + static const struct tidss_plane_feat pfeat = { + .color = { + .encodings = (BIT(DRM_COLOR_YCBCR_BT601) | + BIT(DRM_COLOR_YCBCR_BT709)), + .ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) | + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)), + .default_encoding = DRM_COLOR_YCBCR_BT601, + .default_range = DRM_COLOR_YCBCR_FULL_RANGE, + }, + .blend = { + .global_alpha = true, + }, + }; + + return &pfeat; +} + +static int dispc7_plane_check(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport) +{ + bool lite = dispc->feat->vid_lite[hw_plane]; + u32 fourcc = state->fb->format->format; + bool need_scaling = state->src_w >> 16 != state->crtc_w || + state->src_h >> 16 != state->crtc_h; + struct dispc7_scaling_params scaling; + int ret; + + if (dispc7_fourcc_is_yuv(fourcc)) { + if (!dispc7_find_csc(state->color_encoding, + state->color_range)) { + dev_dbg(dispc->dev, + "%s: Unsupported CSC (%u,%u) for HW plane %u\n", + __func__, state->color_encoding, + state->color_range, hw_plane); + return -EINVAL; + } + } + + if (need_scaling) { + if (lite) { + dev_dbg(dispc->dev, + "%s: Lite plane %u can't scale %ux%u!=%ux%u\n", + __func__, hw_plane, + state->src_w >> 16, state->src_h >> 16, + state->crtc_w, state->crtc_h); + return -EINVAL; + } + ret = dispc7_vid_calc_scaling(dispc, state, &scaling, false); + if (ret) + return ret; + } + + return 0; +} + +static int dispc7_plane_setup(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport) +{ + bool lite = dispc->feat->vid_lite[hw_plane]; + u32 fourcc = state->fb->format->format; + u16 cpp = state->fb->format->cpp[0]; + u32 fb_width = state->fb->pitches[0] / cpp; + dma_addr_t paddr = dispc7_plane_state_paddr(state); + struct dispc7_scaling_params scale; + + dispc7_vid_calc_scaling(dispc, state, &scale, lite); + + dispc7_plane_set_pixel_format(dispc, hw_plane, fourcc); + + dispc7_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff); + dispc7_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32); + dispc7_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff); + dispc7_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32); + + dispc7_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, + (scale.in_w - 1) | ((scale.in_h - 1) << 16)); + + /* For YUV422 format we use the macropixel size for pixel inc */ + if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) + dispc7_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, + pixinc(scale.xinc, cpp * 2)); + else + dispc7_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, + pixinc(scale.xinc, cpp)); + + dispc7_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, + pixinc(1 + (scale.yinc * fb_width - + scale.xinc * scale.in_w), + cpp)); + + if (state->fb->format->num_planes == 2) { + u16 cpp_uv = state->fb->format->cpp[1]; + u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; + dma_addr_t p_uv_addr = dispc7_plane_state_p_uv_addr(state); + + dispc7_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_0, p_uv_addr & 0xffffffff); + dispc7_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_EXT_0, (u64)p_uv_addr >> 32); + dispc7_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_1, p_uv_addr & 0xffffffff); + dispc7_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_EXT_1, (u64)p_uv_addr >> 32); + + dispc7_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, + pixinc(1 + (scale.yinc * fb_width_uv - + scale.xinc * scale.in_w_uv), + cpp_uv)); + } + + if (!lite) { + dispc7_vid_write(dispc, hw_plane, DISPC_VID_SIZE, + (state->crtc_w - 1) | + ((state->crtc_h - 1) << 16)); + + dispc7_vid_set_scaling(dispc, hw_plane, &scale, fourcc); + } + + /* enable YUV->RGB color conversion */ + if (dispc7_fourcc_is_yuv(fourcc)) { + dispc7_vid_csc_setup(dispc, hw_plane, state); + dispc7_vid_csc_enable(dispc, hw_plane, true); + } else { + dispc7_vid_csc_enable(dispc, hw_plane, false); + } + + dispc7_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, + 0xFF & (state->alpha >> 8)); + + /* Set pre-multiplied alpha as default. */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, 22, 22); + + dispc7_ovr_set_plane(dispc, hw_plane, hw_videoport, + state->crtc_x, state->crtc_y, + state->normalized_zpos); + + dispc->plane_data[hw_plane].zorder = state->normalized_zpos; + dispc->plane_data[hw_plane].hw_videoport = hw_videoport; + + return 0; +} + +static int dispc7_plane_enable(struct dispc_device *dispc, + u32 hw_plane, bool enable) +{ + dispc7_ovr_enable_plane(dispc, dispc->plane_data[hw_plane].hw_videoport, + dispc->plane_data[hw_plane].zorder, enable); + + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + + return 0; +} + +static u32 dispc7_vid_get_fifo_size(struct dispc_device *dispc, + u32 hw_plane) +{ + const u32 unit_size = 16; /* 128-bits */ + + return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0) * + unit_size; +} + +static void dispc7_vid_set_mflag_threshold(struct dispc_device *dispc, + u32 hw_plane, u32 low, u32 high) +{ + dispc7_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dispc7_vid_mflag_setup(struct dispc_device *dispc, + u32 hw_plane) +{ + const u32 unit_size = 16; /* 128-bits */ + u32 size = dispc7_vid_get_fifo_size(dispc, hw_plane); + u32 low, high; + + /* + * Simulation team suggests below thesholds: + * HT = fifosize * 5 / 8; + * LT = fifosize * 4 / 8; + */ + + low = size * 4 / 8 / unit_size; + high = size * 5 / 8 / unit_size; + + dispc7_vid_set_mflag_threshold(dispc, hw_plane, low, high); +} + +static void dispc7_mflag_setup(struct dispc_device *dispc) +{ + unsigned int i; + + /* MFLAG_CTRL = ENABLED */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + /* MFLAG_START = MFLAGNORMALSTARTMODE */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + + for (i = 0; i < dispc->feat->num_planes; i++) + dispc7_vid_mflag_setup(dispc, i); +} + +static void dispc7_plane_init(struct dispc_device *dispc) +{ + unsigned int i; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + /* FIFO underflows when scaling if preload is not high enough */ + for (i = 0; i < dispc->feat->num_planes; i++) + if (!dispc->feat->vid_lite[i]) + VID_REG_FLD_MOD(dispc, i, DISPC_VID_PRELOAD, + 0x7FF, 11, 0); +} + +static void dispc7_vp_init(struct dispc_device *dispc) +{ + unsigned int i; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + /* Enable the gamma Shadow bit-field for all VPs*/ + for (i = 0; i < dispc->feat->num_vps; i++) + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); +} + +static void dispc7_initial_config(struct dispc_device *dispc) +{ + dispc7_mflag_setup(dispc); + dispc7_plane_init(dispc); + dispc7_vp_init(dispc); +} + +static int dispc7_get_num_planes(struct dispc_device *dispc) +{ + return dispc->feat->num_planes; +} + +static int dispc7_get_num_vps(struct dispc_device *dispc) +{ + return dispc->feat->num_vps; +} + +static const struct tidss_vp_feat *dispc7_vp_feat(struct dispc_device *dispc, + u32 hw_videoport) +{ + static const struct tidss_vp_feat vp_feat = { + .color = { + .gamma_size = DISPC7_GAMMA_TABLE_SIZE, + .has_ctm = true, + }, + }; + + return &vp_feat; +} + +static void dispc7_vp_write_gamma_table(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = ARRAY_SIZE(dispc->vp_data[hw_videoport].gamma_table); + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + v |= i << 24; + + dispc7_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); + } +} + +static void dispc7_restore_gamma_tables(struct dispc_device *dispc) +{ + unsigned int i; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + for (i = 0; i < dispc->feat->num_vps; i++) + dispc7_vp_write_gamma_table(dispc, i); +} + +static const struct drm_color_lut dispc7_vp_gamma_default_lut[] = { + { .red = 0, .green = 0, .blue = 0, }, + { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, +}; + +static void dispc7_vp_set_gamma(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_color_lut *lut, + unsigned int length) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = ARRAY_SIZE(dispc->vp_data[hw_videoport].gamma_table); + static const unsigned int hwbits = 8; + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", + __func__, hw_videoport, length, hwlen); + + if (lut == NULL || length < 2) { + lut = dispc7_vp_gamma_default_lut; + length = ARRAY_SIZE(dispc7_vp_gamma_default_lut); + } + + for (i = 0; i < length - 1; ++i) { + unsigned int first = i * (hwlen - 1) / (length - 1); + unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); + unsigned int w = last - first; + u16 r, g, b; + unsigned int j; + + if (w == 0) + continue; + + for (j = 0; j <= w; j++) { + r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; + g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; + b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; + + r >>= 16 - hwbits; + g >>= 16 - hwbits; + b >>= 16 - hwbits; + + table[first + j] = (r << (hwbits * 2)) | + (g << hwbits) | b; + } + } + + if (dispc->is_enabled) + dispc7_vp_write_gamma_table(dispc, hw_videoport); +} + +static s16 dispc7_S31_32_to_s2_8(s64 coef) +{ + u64 sign_bit = 1ULL << 63; + u64 cbits = (u64) coef; + s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1FF); + + if (cbits & sign_bit) + ret = -ret; + + return ret; +} + +static void dispc7_cpr_csc_from_ctm(const struct drm_color_ctm *ctm, + struct dispc7_csc_coef *cpr) +{ + memset(cpr, 0, sizeof(*cpr)); + + cpr->to_regval = dispc7_csc_cpr_regval; + cpr->m[CSC_RR] = dispc7_S31_32_to_s2_8(ctm->matrix[0]); + cpr->m[CSC_RG] = dispc7_S31_32_to_s2_8(ctm->matrix[1]); + cpr->m[CSC_RB] = dispc7_S31_32_to_s2_8(ctm->matrix[2]); + cpr->m[CSC_GR] = dispc7_S31_32_to_s2_8(ctm->matrix[3]); + cpr->m[CSC_GG] = dispc7_S31_32_to_s2_8(ctm->matrix[4]); + cpr->m[CSC_GB] = dispc7_S31_32_to_s2_8(ctm->matrix[5]); + cpr->m[CSC_BR] = dispc7_S31_32_to_s2_8(ctm->matrix[6]); + cpr->m[CSC_BG] = dispc7_S31_32_to_s2_8(ctm->matrix[7]); + cpr->m[CSC_BB] = dispc7_S31_32_to_s2_8(ctm->matrix[8]); +} + +static void dispc7_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, + const struct dispc7_csc_coef *csc) +{ + static const u16 dispc_vp_csc_coef_reg[DISPC7_CSC_REGVAL_LEN] = { + DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2, + DISPC_VP_CSC_COEF3, DISPC_VP_CSC_COEF4, DISPC_VP_CSC_COEF5, + DISPC_VP_CSC_COEF6, DISPC_VP_CSC_COEF7, + }; + u32 regval[DISPC7_CSC_REGVAL_LEN]; + unsigned int i; + + csc->to_regval(csc, regval); + + for (i = 0; i < ARRAY_SIZE(regval); i++) + dispc7_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], + regval[i]); +} + +static void dispc7_vp_set_color_mgmt(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_crtc_state *state) +{ + struct drm_color_lut *lut = NULL; + unsigned int length = 0; + bool colorconvenable = false; + + if (!state->color_mgmt_changed) + return; + + if (state->gamma_lut) { + lut = (struct drm_color_lut *) state->gamma_lut->data; + length = state->gamma_lut->length / sizeof(*lut); + } + + if (state->ctm) { + struct drm_color_ctm *ctm = + (struct drm_color_ctm *) state->ctm->data; + struct dispc7_csc_coef cpr; + + dispc7_cpr_csc_from_ctm(ctm, &cpr); + dispc7_vp_write_csc(dispc, hw_videoport, &cpr); + + colorconvenable = true; + } + + dispc7_vp_set_gamma(dispc, hw_videoport, lut, length); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, + colorconvenable, 24, 24); +} + +static void dispc7_vp_setup(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + dispc7_vp_set_default_color(dispc, hw_videoport, 0); + dispc7_vp_set_color_mgmt(dispc, hw_videoport, state); +} + +static int dispc7_init_gamma_tables(struct dispc_device *dispc) +{ + unsigned int i; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + for (i = 0; i < dispc->feat->num_vps; i++) + dispc7_vp_set_gamma(dispc, i, NULL, 0); + + return 0; +} + +static const char *dispc7_plane_name(struct dispc_device *dispc, u32 hw_plane) +{ + if (WARN_ON(hw_plane >= dispc->feat->num_planes)) + return "ERROR"; + + return dispc->feat->vid_name[hw_plane]; +} + +static const char *dispc7_vp_name(struct dispc_device *dispc, u32 hw_videoport) +{ + if (WARN_ON(hw_videoport >= dispc->feat->num_vps)) + return "ERROR"; + + return dispc->feat->vp_name[hw_videoport]; +} + +static int dispc7_runtime_suspend(struct dispc_device *dispc) +{ + dev_dbg(dispc->dev, "suspend\n"); + + dispc->is_enabled = false; + + clk_disable_unprepare(dispc->fclk); + + return 0; +} + +static int dispc7_runtime_resume(struct dispc_device *dispc) +{ + dev_dbg(dispc->dev, "resume\n"); + + clk_prepare_enable(dispc->fclk); + + if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) + dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); + + dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", + dispc7_read(dispc, DSS_REVISION)); + + dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", + REG_GET(dispc, DSS_SYSSTATUS, 1, 1), + REG_GET(dispc, DSS_SYSSTATUS, 2, 2), + REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); + + dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", + REG_GET(dispc, DSS_SYSSTATUS, 5, 5), + REG_GET(dispc, DSS_SYSSTATUS, 6, 6), + REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); + + dev_dbg(dispc->dev, "DISPC IDLE %d\n", + REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); + + dispc7_initial_config(dispc); + + dispc7_restore_gamma_tables(dispc); + + dispc->is_enabled = true; + + return 0; +} + +static int dispc7_modeset_init(struct dispc_device *dispc) +{ + struct tidss_device *tidss = dispc->tidss; + struct device *dev = tidss->dev; + u32 fourccs[ARRAY_SIZE(dispc7_color_formats)]; + unsigned int i; + + struct pipe { + u32 hw_videoport; + struct drm_bridge *bridge; + u32 enc_type; + }; + + u32 max_vps = dispc->feat->num_vps; + u32 max_planes = dispc->feat->num_planes; + + struct pipe pipes[DISPC7_MAX_PORTS]; + u32 num_pipes = 0; + u32 crtc_mask; + + for (i = 0; i < ARRAY_SIZE(fourccs); ++i) + fourccs[i] = dispc7_color_formats[i].fourcc; + + /* first find all the connected panels & bridges */ + + for (i = 0; i < max_vps; i++) { + struct drm_panel *panel; + struct drm_bridge *bridge; + u32 enc_type = DRM_MODE_ENCODER_NONE; + int ret; + + ret = drm_of_find_panel_or_bridge(dev->of_node, i, 0, + &panel, &bridge); + if (ret == -ENODEV) { + dev_dbg(dev, "no panel/bridge for port %d\n", i); + continue; + } else if (ret) { + dev_dbg(dev, "port %d probe returned %d\n", i, ret); + return ret; + } + + if (panel) { + u32 conn_type; + + dev_dbg(dev, "Setting up panel for port %d\n", i); + + switch (dispc->feat->vp_bus_type[i]) { + case DISPC7_VP_OLDI: + enc_type = DRM_MODE_ENCODER_LVDS; + conn_type = DRM_MODE_CONNECTOR_LVDS; + break; + case DISPC7_VP_DPI: + enc_type = DRM_MODE_ENCODER_DPI; + conn_type = DRM_MODE_CONNECTOR_DPI; + break; + default: + conn_type = DRM_MODE_CONNECTOR_Unknown; + break; + } + + bridge = devm_drm_panel_bridge_add(dev, panel, + conn_type); + if (IS_ERR(bridge)) { + dev_err(dev, "failed to set up panel bridge for port %d\n", i); + return PTR_ERR(bridge); + } + } + + pipes[num_pipes].hw_videoport = i; + pipes[num_pipes].bridge = bridge; + pipes[num_pipes].enc_type = enc_type; + num_pipes++; + } + + /* all planes can be on any crtc */ + crtc_mask = (1 << num_pipes) - 1; + + /* then create a plane, a crtc and an encoder for each panel/bridge */ + + for (i = 0; i < num_pipes; ++i) { + struct tidss_plane *tplane; + struct tidss_crtc *tcrtc; + struct drm_encoder *enc; + u32 hw_plane_id = tidss->num_planes; + int ret; + + tplane = tidss_plane_create(tidss, hw_plane_id, + DRM_PLANE_TYPE_PRIMARY, crtc_mask, + fourccs, ARRAY_SIZE(fourccs)); + if (IS_ERR(tplane)) { + dev_err(tidss->dev, "plane create failed\n"); + return PTR_ERR(tplane); + } + + tidss->planes[tidss->num_planes++] = &tplane->plane; + + tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, + &tplane->plane); + if (IS_ERR(tcrtc)) { + dev_err(tidss->dev, "crtc create failed\n"); + return PTR_ERR(tcrtc); + } + + tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc; + + enc = tidss_encoder_create(tidss, pipes[i].enc_type, + 1 << tcrtc->crtc.index); + if (IS_ERR(enc)) { + dev_err(tidss->dev, "encoder create failed\n"); + return PTR_ERR(enc); + } + + ret = drm_bridge_attach(enc, pipes[i].bridge, NULL); + if (ret) { + dev_err(tidss->dev, "bridge attach failed: %d\n", ret); + return ret; + } + } + + /* create overlay planes of the leftover planes */ + + while (tidss->num_planes < max_planes) { + struct tidss_plane *tplane; + u32 hw_plane_id = tidss->num_planes; + + tplane = tidss_plane_create(tidss, hw_plane_id, + DRM_PLANE_TYPE_OVERLAY, crtc_mask, + fourccs, ARRAY_SIZE(fourccs)); + + if (IS_ERR(tplane)) { + dev_err(tidss->dev, "plane create failed\n"); + return PTR_ERR(tplane); + } + + tidss->planes[tidss->num_planes++] = &tplane->plane; + } + + return 0; +} + +static void dispc7_remove(struct dispc_device *dispc) +{ + struct device *dev = dispc->dev; + + dev_dbg(dev, "%s\n", __func__); + + dispc->tidss->dispc_ops = NULL; + dispc->tidss->dispc = NULL; +} + +static const struct tidss_dispc_ops dispc7_ops = { + .read_and_clear_irqstatus = dispc7_read_and_clear_irqstatus, + .write_irqenable = dispc7_write_irqenable, + + .get_num_vps = dispc7_get_num_vps, + .vp_name = dispc7_vp_name, + .vp_feat = dispc7_vp_feat, + .vp_mode_valid = dispc7_vp_mode_valid, + .vp_check = dispc7_vp_check, + .vp_setup = dispc7_vp_setup, + .vp_prepare = dispc7_vp_prepare, + .vp_enable = dispc7_vp_enable, + .vp_disable = dispc7_vp_disable, + .vp_unprepare = dispc7_vp_unprepare, + .vp_go_busy = dispc7_vp_go_busy, + .vp_go = dispc7_vp_go, + + .vp_set_clk_rate = dispc7_vp_set_clk_rate, + .vp_enable_clk = dispc7_vp_enable_clk, + .vp_disable_clk = dispc7_vp_disable_clk, + + .get_num_planes = dispc7_get_num_planes, + .plane_name = dispc7_plane_name, + .plane_feat = dispc7_plane_feat, + .plane_enable = dispc7_plane_enable, + .plane_check = dispc7_plane_check, + .plane_setup = dispc7_plane_setup, + + .runtime_get = dispc7_runtime_get, + .runtime_put = dispc7_runtime_put, + + .runtime_suspend = dispc7_runtime_suspend, + .runtime_resume = dispc7_runtime_resume, + + .remove = dispc7_remove, + + .modeset_init = dispc7_modeset_init, +}; + +static int dispc7_iomap_resource(struct platform_device *pdev, const char *name, + void __iomem **base) +{ + struct resource *res; + void __iomem *b; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (!res) { + dev_err(&pdev->dev, "cannot get mem resource '%s'\n", name); + return -EINVAL; + } + + b = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(b)) { + dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); + return PTR_ERR(b); + } + + *base = b; + + return 0; +} + +int dispc7_init(struct tidss_device *tidss) +{ + struct device *dev = tidss->dev; + struct platform_device *pdev = to_platform_device(dev); + struct dispc_device *dispc; + const struct dispc7_features *feat; + unsigned int i; + int r = 0; + + dev_dbg(dev, "%s\n", __func__); + + feat = of_match_device(dispc7_of_table, dev)->data; + + dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); + if (!dispc) + return -ENOMEM; + + dispc->tidss = tidss; + dispc->dev = dev; + dispc->feat = feat; + + r = dispc7_iomap_resource(pdev, "common", &dispc->base_common); + if (r) + return r; + + for (i = 0; i < dispc->feat->num_planes; i++) { + r = dispc7_iomap_resource(pdev, dispc->feat->vid_name[i], + &dispc->base_vid[i]); + dev_dbg(dev, "%s: %u %s %d\n", __func__, + i, dispc->feat->vid_name[i], r); + if (r) + return r; + } + + for (i = 0; i < dispc->feat->num_vps; i++) { + struct clk *clk; + + r = dispc7_iomap_resource(pdev, dispc->feat->ovr_name[i], + &dispc->base_ovr[i]); + dev_dbg(dev, "%s: %u %s %d\n", __func__, + i, dispc->feat->ovr_name[i], r); + if (r) + return r; + + r = dispc7_iomap_resource(pdev, dispc->feat->vp_name[i], + &dispc->base_vp[i]); + dev_dbg(dev, "%s: %u %s %d\n", __func__, + i, dispc->feat->vp_name[i], r); + if (r) + return r; + + clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); + if (IS_ERR(clk)) { + dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__, + dispc->feat->vpclk_name[i], PTR_ERR(clk)); + return PTR_ERR(clk); + } + dispc->vp_clk[i] = clk; + } + + dispc->syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); + if (IS_ERR(dispc->syscon)) { + dev_err(dev, "%s: syscon_regmap_lookup_by_phandle failed %ld\n", + __func__, PTR_ERR(dispc->syscon)); + return PTR_ERR(dispc->syscon); + } + + dispc->fclk = devm_clk_get(dev, "fck"); + if (IS_ERR(dispc->fclk)) { + dev_err(dev, "Failed to get fclk\n"); + return PTR_ERR(dispc->fclk); + } + dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); + + r = dispc7_init_gamma_tables(dispc); + if (r) + return r; + + tidss->dispc_ops = &dispc7_ops; + tidss->dispc = dispc; + + return 0; +} diff --git a/drivers/gpu/drm/tidss/tidss_dispc7.h b/drivers/gpu/drm/tidss/tidss_dispc7.h new file mode 100644 index 0000000..52f0965 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_dispc7.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha + */ + +#ifndef __TIDSS_DISPC7_H +#define __TIDSS_DISPC7_H + +#define DISPC7_MAX_PORTS 4 +#define DISPC7_MAX_PLANES 4 + +struct dispc7_features_scaling { + u32 in_width_max_5tap_rgb; + u32 in_width_max_3tap_rgb; + u32 in_width_max_5tap_yuv; + u32 in_width_max_3tap_yuv; + u32 upscale_limit; + u32 downscale_limit_5tap; + u32 downscale_limit_3tap; + u32 xinc_max; +}; + +enum dispc7_vp_bus_type { + DISPC7_VP_DPI, + DISPC7_VP_OLDI, +}; + +struct dispc7_features { + /* XXX should these come from the .dts? Min pclk is not feature of DSS IP */ + unsigned long min_pclk; + unsigned long max_pclk; + + struct dispc7_features_scaling scaling; + + u32 num_vps; + const char *vp_name[DISPC7_MAX_PORTS]; /* Should match dt reg names */ + const char *ovr_name[DISPC7_MAX_PORTS]; /* Should match dt reg names */ + const char *vpclk_name[DISPC7_MAX_PORTS]; /* Should match dt clk names */ + const enum dispc7_vp_bus_type vp_bus_type[DISPC7_MAX_PORTS]; + u32 num_planes; + const char *vid_name[DISPC7_MAX_PLANES]; /* Should match dt reg names */ + bool vid_lite[DISPC7_MAX_PLANES]; +}; + +#define DSS_REVISION 0x4 +#define DSS_SYSCONFIG 0x8 +#define DSS_SYSSTATUS 0x20 +#define DISPC_IRQ_EOI 0x24 +#define DISPC_IRQSTATUS_RAW 0x28 +#define DISPC_IRQSTATUS 0x2c +#define DISPC_IRQENABLE_SET 0x30 +#define DISPC_IRQENABLE_CLR 0x40 +#define DISPC_VID_IRQENABLE(n) (0x44 + (n) * 4) +#define DISPC_VID_IRQSTATUS(n) (0x58 + (n) * 4) +#define DISPC_VP_IRQENABLE(n) (0x70 + (n) * 4) +#define DISPC_VP_IRQSTATUS(n) (0x7c + (n) * 4) + +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x90 +#define DISPC_GLOBAL_OUTPUT_ENABLE 0x94 +#define DISPC_GLOBAL_BUFFER 0x98 +#define DSS_CBA_CFG 0x9c +#define DISPC_DBG_CONTROL 0xa0 +#define DISPC_DBG_STATUS 0xa4 +#define DISPC_CLKGATING_DISABLE 0xa8 +#define DISPC_SECURE_DISABLE 0xac + +/* COMMON1 not implemented */ + +/* VID */ + +#define DISPC_VID_ACCUH_0 0x0 +#define DISPC_VID_ACCUH_1 0x4 +#define DISPC_VID_ACCUH2_0 0x8 +#define DISPC_VID_ACCUH2_1 0xc +#define DISPC_VID_ACCUV_0 0x10 +#define DISPC_VID_ACCUV_1 0x14 +#define DISPC_VID_ACCUV2_0 0x18 +#define DISPC_VID_ACCUV2_1 0x1c +#define DISPC_VID_ATTRIBUTES 0x20 +#define DISPC_VID_ATTRIBUTES2 0x24 +#define DISPC_VID_BA_0 0x28 +#define DISPC_VID_BA_1 0x2c +#define DISPC_VID_BA_UV_0 0x30 +#define DISPC_VID_BA_UV_1 0x34 +#define DISPC_VID_BUF_SIZE_STATUS 0x38 +#define DISPC_VID_BUF_THRESHOLD 0x3c +#define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) + +#define DISPC_VID_FIRH 0x5c +#define DISPC_VID_FIRH2 0x60 +#define DISPC_VID_FIRV 0x64 +#define DISPC_VID_FIRV2 0x68 + +#define DISPC_VID_FIR_COEFS_H0 0x6c +#define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) +#define DISPC_VID_FIR_COEFS_H0_C 0x90 +#define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_H12 0xb4 +#define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) +#define DISPC_VID_FIR_COEFS_H12_C 0xf4 +#define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_V0 0x134 +#define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) +#define DISPC_VID_FIR_COEFS_V0_C 0x158 +#define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_V12 0x17c +#define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) +#define DISPC_VID_FIR_COEFS_V12_C 0x1bc +#define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) + +#define DISPC_VID_GLOBAL_ALPHA 0x1fc +#define DISPC_VID_MFLAG_THRESHOLD 0x208 +#define DISPC_VID_PICTURE_SIZE 0x20c +#define DISPC_VID_PIXEL_INC 0x210 +#define DISPC_VID_PRELOAD 0x218 +#define DISPC_VID_ROW_INC 0x21c +#define DISPC_VID_SIZE 0x220 +#define DISPC_VID_BA_EXT_0 0x22c +#define DISPC_VID_BA_EXT_1 0x230 +#define DISPC_VID_BA_UV_EXT_0 0x234 +#define DISPC_VID_BA_UV_EXT_1 0x238 +#define DISPC_VID_CSC_COEF7 0x23c +#define DISPC_VID_ROW_INC_UV 0x248 +#define DISPC_VID_CLUT 0x260 +#define DISPC_VID_SAFETY_ATTRIBUTES 0x2a0 +#define DISPC_VID_SAFETY_CAPT_SIGNATURE 0x2a4 +#define DISPC_VID_SAFETY_POSITION 0x2a8 +#define DISPC_VID_SAFETY_REF_SIGNATURE 0x2ac +#define DISPC_VID_SAFETY_SIZE 0x2b0 +#define DISPC_VID_SAFETY_LFSR_SEED 0x2b4 +#define DISPC_VID_LUMAKEY 0x2b8 + +/* OVR */ + +#define DISPC_OVR_CONFIG 0x0 +#define DISPC_OVR_DEFAULT_COLOR 0x8 +#define DISPC_OVR_DEFAULT_COLOR2 0xc +#define DISPC_OVR_TRANS_COLOR_MAX 0x10 +#define DISPC_OVR_TRANS_COLOR_MAX2 0x14 +#define DISPC_OVR_TRANS_COLOR_MIN 0x18 +#define DISPC_OVR_TRANS_COLOR_MIN2 0x1c +#define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) + +/* VP */ + +#define DISPC_VP_CONFIG 0x0 +#define DISPC_VP_CONTROL 0x4 +#define DISPC_VP_CSC_COEF0 0x8 +#define DISPC_VP_CSC_COEF1 0xc +#define DISPC_VP_CSC_COEF2 0x10 +#define DISPC_VP_DATA_CYCLE_0 0x14 +#define DISPC_VP_DATA_CYCLE_1 0x18 +#define DISPC_VP_DATA_CYCLE_2 0x1c +#define DISPC_VP_LINE_NUMBER 0x44 +#define DISPC_VP_POL_FREQ 0x4c +#define DISPC_VP_SIZE_SCREEN 0x50 +#define DISPC_VP_TIMING_H 0x54 +#define DISPC_VP_TIMING_V 0x58 +#define DISPC_VP_CSC_COEF3 0x5c +#define DISPC_VP_CSC_COEF4 0x60 +#define DISPC_VP_CSC_COEF5 0x64 +#define DISPC_VP_CSC_COEF6 0x68 +#define DISPC_VP_CSC_COEF7 0x6c +#define DISPC_VP_SAFETY_ATTRIBUTES_0 0x70 +#define DISPC_VP_SAFETY_ATTRIBUTES_1 0x74 +#define DISPC_VP_SAFETY_ATTRIBUTES_2 0x78 +#define DISPC_VP_SAFETY_ATTRIBUTES_3 0x7c +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 0x90 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 0x94 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 0x98 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 0x9c +#define DISPC_VP_SAFETY_POSITION_0 0xb0 +#define DISPC_VP_SAFETY_POSITION_1 0xb4 +#define DISPC_VP_SAFETY_POSITION_2 0xb8 +#define DISPC_VP_SAFETY_POSITION_3 0xbc +#define DISPC_VP_SAFETY_REF_SIGNATURE_0 0xd0 +#define DISPC_VP_SAFETY_REF_SIGNATURE_1 0xd4 +#define DISPC_VP_SAFETY_REF_SIGNATURE_2 0xd8 +#define DISPC_VP_SAFETY_REF_SIGNATURE_3 0xdc +#define DISPC_VP_SAFETY_SIZE_0 0xf0 +#define DISPC_VP_SAFETY_SIZE_1 0xf4 +#define DISPC_VP_SAFETY_SIZE_2 0xf8 +#define DISPC_VP_SAFETY_SIZE_3 0xfc +#define DISPC_VP_SAFETY_LFSR_SEED 0x110 +#define DISPC_VP_GAMMA_TABLE 0x120 +#define DISPC_VP_DSS_OLDI_CFG 0x160 +#define DISPC_VP_DSS_OLDI_STATUS 0x164 +#define DISPC_VP_DSS_OLDI_LB 0x168 + +/* CTRL_MMR0 access trough syscon */ +#define CTRLMMR0P1_OLDI_DAT0_IO_CTRL 0x41E0 +#define CTRLMMR0P1_OLDI_DAT1_IO_CTRL 0x41E4 +#define CTRLMMR0P1_OLDI_DAT2_IO_CTRL 0x41E8 +#define CTRLMMR0P1_OLDI_DAT3_IO_CTRL 0x41EC +#define CTRLMMR0P1_OLDI_CLK_IO_CTRL 0x41F0 + +#define CTRLMMR0P1_OLDI_PWRDN_TX BIT(8) + +#endif /* __TIDSS_DISPC7_H */ diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index 8485f9a..27f78db 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -274,12 +274,24 @@ static int tidss_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_DRM_TIDSS_DSS6 static const struct tidss_features tidss_k2g_features = { .dispc_init = dispc6_init, }; +#endif +#ifdef CONFIG_DRM_TIDSS_DSS7 +static const struct tidss_features tidss_am6_features = { + .dispc_init = dispc7_init, +}; +#endif static const struct of_device_id tidss_of_table[] = { +#ifdef CONFIG_DRM_TIDSS_DSS6 { .compatible = "ti,k2g-dss", .data = &tidss_k2g_features }, +#endif +#ifdef CONFIG_DRM_TIDSS_DSS7 + { .compatible = "ti,am6-dss", .data = &tidss_am6_features }, +#endif { } }; diff --git a/drivers/gpu/drm/tidss/tidss_scale_coefs.c b/drivers/gpu/drm/tidss/tidss_scale_coefs.c new file mode 100644 index 0000000..2cc5f67 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_scale_coefs.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha + */ + +#include +#include +#include "tidss_scale_coefs.h" + +/* + * These are interpolated with a custom python script from DSS5 + * (drivers/gpu/drm/omapdrm/dss/dispc_coef.c) coefficients. + */ +static const struct tidss_scale_coefs coef5_M32 = { + .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, }, + .c1 = { 132, 138, 144, 150, 156, 162, 168, 174, 76, 84, 92, 98, 104, 110, 116, 124, }, + .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, }, +}; +static const struct tidss_scale_coefs coef5_M26 = { + .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, }, + .c1 = { 132, 138, 144, 152, 160, 166, 172, 178, 72, 80, 88, 94, 100, 108, 116, 124, }, + .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, }, +}; +static const struct tidss_scale_coefs coef5_M22 = { + .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, }, + .c1 = { 132, 140, 148, 156, 164, 172, 180, 186, 64, 72, 80, 88, 96, 104, 112, 122, }, + .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, }, +}; +static const struct tidss_scale_coefs coef5_M19 = { + .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, }, + .c1 = { 128, 140, 152, 160, 168, 176, 184, 192, 56, 64, 72, 82, 92, 100, 108, 118, }, + .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, }, +}; +static const struct tidss_scale_coefs coef5_M16 = { + .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, }, + .c1 = { 124, 138, 152, 164, 176, 186, 196, 206, 40, 48, 56, 68, 80, 90, 100, 112, }, + .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, }, +}; +static const struct tidss_scale_coefs coef5_M14 = { + .c2 = { -8, -6, -4, -2, 0, 6, 12, 18, 0, -2, -4, -6, -8, -8, -8, -8, }, + .c1 = { 120, 134, 148, 164, 180, 194, 208, 220, 24, 32, 40, 52, 64, 78, 92, 106, }, + .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, }, +}; +static const struct tidss_scale_coefs coef5_M13 = { + .c2 = { -12, -12, -12, -10, -8, -4, 0, 6, 0, -2, -4, -6, -8, -10, -12, -12, }, + .c1 = { 112, 130, 148, 164, 180, 196, 212, 228, 12, 22, 32, 44, 56, 70, 84, 98, }, + .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, }, +}; +static const struct tidss_scale_coefs coef5_M12 = { + .c2 = { -16, -18, -20, -18, -16, -14, -12, -6, 0, -2, -4, -6, -8, -10, -12, -14, }, + .c1 = { 104, 124, 144, 164, 184, 202, 220, 238, 0, 10, 20, 30, 40, 56, 72, 88, }, + .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, }, +}; +static const struct tidss_scale_coefs coef5_M11 = { + .c2 = { -20, -22, -24, -24, -24, -24, -24, -20, 0, -2, -4, -6, -8, -10, -12, -16, }, + .c1 = { 92, 114, 136, 158, 180, 204, 228, 250, -16, -8, 0, 12, 24, 38, 52, 72, }, + .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, }, +}; +static const struct tidss_scale_coefs coef5_M10 = { + .c2 = { -16, -20, -24, -28, -32, -34, -36, -34, 0, 0, 0, -2, -4, -8, -12, -14, }, + .c1 = { 72, 96, 120, 148, 176, 204, 232, 260, -32, -26, -20, -10, 0, 16, 32, 52, }, + .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, }, +}; +static const struct tidss_scale_coefs coef5_M9 = { + .c2 = { -12, -18, -24, -28, -32, -38, -44, -46, 0, 2, 4, 2, 0, -2, -4, -8, }, + .c1 = { 40, 68, 96, 128, 160, 196, 232, 268, -48, -46, -44, -36, -28, -14, 0, 20, }, + .c0 = { 456, 450, 444, 428, 412, 388, 364, 334, 304, }, +}; +static const struct tidss_scale_coefs coef5_M8 = { + .c2 = { 0, -4, -8, -16, -24, -32, -40, -48, 0, 2, 4, 6, 8, 6, 4, 2, }, + .c1 = { 0, 28, 56, 94, 132, 176, 220, 266, -56, -60, -64, -62, -60, -50, -40, -20, }, + .c0 = { 512, 506, 500, 478, 456, 424, 392, 352, 312, }, +}; +static const struct tidss_scale_coefs coef3_M32 = { + .c1 = { 108, 92, 76, 62, 48, 36, 24, 140, 256, 236, 216, 198, 180, 162, 144, 126, }, + .c0 = { 296, 294, 292, 288, 284, 278, 272, 136, 256, }, +}; +static const struct tidss_scale_coefs coef3_M26 = { + .c1 = { 104, 90, 76, 60, 44, 32, 20, 138, 256, 236, 216, 198, 180, 160, 140, 122, }, + .c0 = { 304, 300, 296, 292, 288, 282, 276, 138, 256, }, +}; +static const struct tidss_scale_coefs coef3_M22 = { + .c1 = { 100, 84, 68, 54, 40, 30, 20, 138, 256, 236, 216, 196, 176, 156, 136, 118, }, + .c0 = { 312, 310, 308, 302, 296, 286, 276, 138, 256, }, +}; +static const struct tidss_scale_coefs coef3_M19 = { + .c1 = { 96, 80, 64, 50, 36, 26, 16, 136, 256, 236, 216, 194, 172, 152, 132, 114, }, + .c0 = { 320, 318, 316, 310, 304, 292, 280, 140, 256, }, +}; +static const struct tidss_scale_coefs coef3_M16 = { + .c1 = { 88, 72, 56, 44, 32, 22, 12, 134, 256, 234, 212, 190, 168, 148, 128, 108, }, + .c0 = { 336, 332, 328, 320, 312, 300, 288, 144, 256, }, +}; +static const struct tidss_scale_coefs coef3_M14 = { + .c1 = { 80, 64, 48, 36, 24, 16, 8, 132, 256, 232, 208, 186, 164, 142, 120, 100, }, + .c0 = { 352, 348, 344, 334, 324, 310, 296, 148, 256, }, +}; +static const struct tidss_scale_coefs coef3_M13 = { + .c1 = { 72, 56, 40, 30, 20, 12, 4, 130, 256, 232, 208, 184, 160, 136, 112, 92, }, + .c0 = { 368, 364, 360, 346, 332, 316, 300, 150, 256, }, +}; +static const struct tidss_scale_coefs coef3_M12 = { + .c1 = { 64, 50, 36, 26, 16, 10, 4, 130, 256, 230, 204, 178, 152, 128, 104, 84, }, + .c0 = { 384, 378, 372, 358, 344, 324, 304, 152, 256, }, +}; +static const struct tidss_scale_coefs coef3_M11 = { + .c1 = { 56, 40, 24, 16, 8, 4, 0, 128, 256, 228, 200, 172, 144, 120, 96, 76, }, + .c0 = { 400, 396, 392, 376, 360, 336, 312, 156, 256, }, +}; +static const struct tidss_scale_coefs coef3_M10 = { + .c1 = { 40, 26, 12, 6, 0, -2, -4, 126, 256, 226, 196, 166, 136, 110, 84, 62, }, + .c0 = { 432, 424, 416, 396, 376, 348, 320, 160, 256, }, +}; +static const struct tidss_scale_coefs coef3_M9 = { + .c1 = { 24, 12, 0, -4, -8, -8, -8, 124, 256, 222, 188, 154, 120, 92, 64, 44, }, + .c0 = { 464, 456, 448, 424, 400, 366, 332, 166, 256, }, +}; +static const struct tidss_scale_coefs coef3_M8 = { + .c1 = { 0, -8, -16, -16, -16, -12, -8, 124, 256, 214, 172, 134, 96, 66, 36, 18, }, + .c0 = { 512, 502, 492, 462, 432, 390, 348, 174, 256, }, +}; + +/* Nearest neigbor coefficients for testing */ +static const struct tidss_scale_coefs coefs_null = { + .c2 = { 0 }, + .c1 = { 0 }, + .c0 = { 512, 512, 512, 512, 512, 512, 512, 512, 256, }, +}; + +const struct tidss_scale_coefs *tidss_get_scale_coefs(struct device *dev, + u32 firinc, + bool five_taps) +{ + int i; + int inc; + static const struct { + int Mmin; + int Mmax; + const struct tidss_scale_coefs *coef3; + const struct tidss_scale_coefs *coef5; + const char *name; + } coefs[] = { + { 27, 32, &coef3_M32, &coef5_M32, "M32" }, + { 23, 26, &coef3_M26, &coef5_M26, "M26" }, + { 20, 22, &coef3_M22, &coef5_M22, "M22" }, + { 17, 19, &coef3_M19, &coef5_M19, "M19" }, + { 15, 16, &coef3_M16, &coef5_M16, "M16" }, + { 14, 14, &coef3_M14, &coef5_M14, "M14" }, + { 13, 13, &coef3_M13, &coef5_M13, "M13" }, + { 12, 12, &coef3_M12, &coef5_M12, "M12" }, + { 11, 11, &coef3_M11, &coef5_M11, "M11" }, + { 10, 10, &coef3_M10, &coef5_M10, "M10" }, + { 9, 9, &coef3_M9, &coef5_M9, "M9" }, + { 4, 8, &coef3_M8, &coef5_M8, "M8" }, + /* + * When upscaling more than two times, blockiness and outlines + * around the image are observed when M8 tables are used. M11, + * M16 and M19 tables are used to prevent this. + */ + { 3, 3, &coef3_M11, &coef5_M11, "M11" }, + { 2, 2, &coef3_M16, &coef5_M16, "M16" }, + { 0, 1, &coef3_M19, &coef5_M19, "M19" }, + }; + + /* + * inc is result of 0x200000 * in_size / out_size. This dividing + * by 0x40000 scales it down to 8 * in_size / out_size. After + * division the actual scaling factor is 8/inc. + */ + inc = firinc / 0x40000; + for (i = 0; i < ARRAY_SIZE(coefs); ++i) { + if (inc >= coefs[i].Mmin && inc <= coefs[i].Mmax) { + if (five_taps) + return coefs[i].coef5; + else + return coefs[i].coef3; + } + } + + dev_err(dev, "%s: Coefficients not found for firinc 0x%08x, inc %d\n", + __func__, firinc, inc); + + return NULL; +} diff --git a/drivers/gpu/drm/tidss/tidss_scale_coefs.h b/drivers/gpu/drm/tidss/tidss_scale_coefs.h new file mode 100644 index 0000000..64b5af5 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_scale_coefs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha + */ + +#ifndef __TIDSS_DISPC_COEF_H__ +#define __TIDSS_DISPC_COEF_H__ + +#include + +struct tidss_scale_coefs { + s16 c2[16]; + s16 c1[16]; + u16 c0[9]; +}; + +const struct tidss_scale_coefs *tidss_get_scale_coefs(struct device *dev, + u32 firinc, + bool five_taps); + +#endif