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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5157; H:AM6PR04MB4007.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 2fkKl+6LRzqpZVnti+xpkUtM/xV1f3E4h19Sy6ZFZyKUxOK8X8p2LWlfN0twDSZ9W5JPIWpn/ja/sKYkTeRML+oHxwwcINnYm+j8AB6ghZ0CO85Biqn1ro2ZTNvoeff3gDNzzmST9Jqy6axD1Qvzk9V4M/t5EG64iwMwEd1OBk4HMFsL3r0jQbn01WPWAJgPM6sSPLExxGUuU24hr+htvOhV30dMCEEA+N4/YmeolZEoia/IwdaUm09QGICvbqwejRanDvdBLy3b0zJ4fhnOTY/JDktIwhds6MRVSM17ys3SrYLVmrM6B1KmleTQwZJM spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60541cf4-5102-4c5e-f733-08d6763cad5f X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2019 14:13:49.2322 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5157 X-Mailman-Approved-At: Thu, 10 Jan 2019 08:34:06 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anson Huang , David Airlie , "linux-kernel@vger.kernel.org" , Fabio Estevam , "dri-devel@lists.freedesktop.org" , "kernel@pengutronix.de" , Robert Chiras , Shawn Guo , dl-linux-imx Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF is enabled, since it comes up with default value of 1 (this behaviour has been seen on some imx8 platforms). In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting its value. Signed-off-by: Robert Chiras --- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index b9437c7..c5689c2 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -231,6 +231,13 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) clk_prepare_enable(mxsfb->clk); if (mxsfb->devdata->ipversion >= 4) { + /* + * On some platforms, bit 21 is defaulted to 1, which may alter + * the below setting. So, to make sure we have the right setting + * clear all the bits for CTRL2_OUTSTANDING_REQS. + */ + writel(CTRL2_OUTSTANDING_REQS(0x7), + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR); writel(CTRL2_OUTSTANDING_REQS(REQ_16), mxsfb->base + LCDC_V4_CTRL2 + REG_SET); /* Assert LCD Reset bit */