| Message ID | 1552937931-23050-5-git-send-email-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/6] dt-bindings: gpu: mali-utgard: add hisilicon, hi6220-mali compatible | expand |
Hi Peter, On Mon, 2019-03-18 at 19:38 +0000, Peter Griffin wrote: > This is required to bring Mali450 gpu out of reset. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/reset/hisilicon/hi6220_reset.c | 51 +++++++++++++++++++++++++++++++++- > 1 file changed, 50 insertions(+), 1 deletion(-) > > diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c > index d5e5229..0cd5f92 100644 > --- a/drivers/reset/hisilicon/hi6220_reset.c > +++ b/drivers/reset/hisilicon/hi6220_reset.c > @@ -36,6 +36,7 @@ > enum hi6220_reset_ctrl_type { > PERIPHERAL, > MEDIA, > + AO, > }; > > struct hi6220_reset_data { > @@ -95,6 +96,47 @@ static const struct reset_control_ops hi6220_media_reset_ops = { > .deassert = hi6220_media_deassert, > }; > > +#define AO_SCTRL_SC_PW_CLKEN0 0x800 > +#define AO_SCTRL_SC_PW_CLKDIS0 0x804 > + > +#define AO_SCTRL_SC_PW_RSTEN0 0x810 > +#define AO_SCTRL_SC_PW_RSTDIS0 0x814 > + > +#define AO_SCTRL_SC_PW_ISOEN0 0x820 > +#define AO_SCTRL_SC_PW_ISODIS0 0x824 > +#define AO_MAX_INDEX 12 > + > +static int hi6220_ao_assert(struct reset_controller_dev *rc_dev, > + unsigned long idx) > +{ > + struct hi6220_reset_data *data = to_reset_data(rc_dev); > + struct regmap *regmap = data->regmap; > + int ret; > + > + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx)); > + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx)); > + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx)); What if two regmap_writes return a different error code? Better check for ret and return individually. Also, no need to issue two more writes if the first one failed. > + return ret; > +} > + > +static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev, > + unsigned long idx) > +{ > + struct hi6220_reset_data *data = to_reset_data(rc_dev); > + struct regmap *regmap = data->regmap; > + int ret; > + > + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx)); > + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx)); > + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx)); Same as above. Otherwise this looks fine. With this fixed, I could pick up patches 2, 4, and 5. regards Philipp
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c index d5e5229..0cd5f92 100644 --- a/drivers/reset/hisilicon/hi6220_reset.c +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -36,6 +36,7 @@ enum hi6220_reset_ctrl_type { PERIPHERAL, MEDIA, + AO, }; struct hi6220_reset_data { @@ -95,6 +96,47 @@ static const struct reset_control_ops hi6220_media_reset_ops = { .deassert = hi6220_media_deassert, }; +#define AO_SCTRL_SC_PW_CLKEN0 0x800 +#define AO_SCTRL_SC_PW_CLKDIS0 0x804 + +#define AO_SCTRL_SC_PW_RSTEN0 0x810 +#define AO_SCTRL_SC_PW_RSTDIS0 0x814 + +#define AO_SCTRL_SC_PW_ISOEN0 0x820 +#define AO_SCTRL_SC_PW_ISODIS0 0x824 +#define AO_MAX_INDEX 12 + +static int hi6220_ao_assert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + int ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx)); + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx)); + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx)); + return ret; +} + +static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + int ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx)); + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx)); + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx)); + return ret; +} + +static const struct reset_control_ops hi6220_ao_reset_ops = { + .assert = hi6220_ao_assert, + .deassert = hi6220_ao_deassert, +}; + static int hi6220_reset_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -120,9 +162,12 @@ static int hi6220_reset_probe(struct platform_device *pdev) if (type == MEDIA) { data->rc_dev.ops = &hi6220_media_reset_ops; data->rc_dev.nr_resets = MEDIA_MAX_INDEX; - } else { + } else if (type == PERIPHERAL) { data->rc_dev.ops = &hi6220_peripheral_reset_ops; data->rc_dev.nr_resets = PERIPH_MAX_INDEX; + } else { + data->rc_dev.ops = &hi6220_ao_reset_ops; + data->rc_dev.nr_resets = AO_MAX_INDEX; } return reset_controller_register(&data->rc_dev); @@ -137,6 +182,10 @@ static const struct of_device_id hi6220_reset_match[] = { .compatible = "hisilicon,hi6220-mediactrl", .data = (void *)MEDIA, }, + { + .compatible = "hisilicon,hi6220-aoctrl", + .data = (void *)AO, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, hi6220_reset_match);
This is required to bring Mali450 gpu out of reset. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/reset/hisilicon/hi6220_reset.c | 51 +++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-)