From patchwork Thu Mar 28 20:16:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10875787 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0A17186D for ; Thu, 28 Mar 2019 19:51:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89F0428E4A for ; Thu, 28 Mar 2019 19:51:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7E43728E56; Thu, 28 Mar 2019 19:51:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2FA5628E4A for ; Thu, 28 Mar 2019 19:51:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 425686E806; Thu, 28 Mar 2019 19:51:35 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5ADC6E81A; Thu, 28 Mar 2019 19:51:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2019 12:51:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,281,1549958400"; d="scan'208";a="138247648" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga007.fm.intel.com with ESMTP; 28 Mar 2019 12:51:15 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [v7 11/16] drm/i915/icl: Enable Plane Degamma Date: Fri, 29 Mar 2019 01:46:09 +0530 Message-Id: <1553804174-2651-12-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1553804174-2651-1-git-send-email-uma.shankar@intel.com> References: <1553804174-2651-1-git-send-email-uma.shankar@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, emil.l.velikov@gmail.com, Uma Shankar , maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable Plane Degamma for ICL. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index afb1d00..504c046 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -615,6 +615,89 @@ static void broadwell_load_plane_luts(const struct drm_plane_state *state) INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); } +static void icl_load_plane_degamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + lut_size = 128; + if (state->degamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(lut[i].red, + 24); + u32 lut_val = (word & 0x7ffffffff) >> 8; + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + drm_color_lut_extract_ext(lut[i].red, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + drm_color_lut_extract_ext(lut[i].green, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + drm_color_lut_extract_ext(lut[i].blue, 24)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + (1 << 24) - 1); + } + } else { + lut_size = 32; + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), + lut[i].green); + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } + } +} + +/* Loads the palette/gamma unit for the CRTC on Gen11+. */ +static void icl_load_plane_luts(const struct drm_plane_state *state) +{ + icl_load_plane_degamma_lut(state, 0); +} + static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -978,6 +1061,9 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_commit = ilk_color_commit; } + if (INTEL_GEN(dev_priv) >= 11) + dev_priv->display.load_plane_luts = icl_load_plane_luts; + /* Enable color management support when we have degamma & gamma LUTs. */ if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)