diff mbox series

[v2,2/7] drm/i915: Define color lut range structure

Message ID 1554139811-13280-3-git-send-email-uma.shankar@intel.com (mailing list archive)
State New, archived
Headers show
Series Add Multi Segment Gamma Support | expand

Commit Message

Shankar, Uma April 1, 2019, 5:30 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This defines the color lut ranges for 10bit and multi
segmented gamma range for ICL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 301 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 297 insertions(+), 4 deletions(-)

Comments

Ville Syrjälä April 8, 2019, 10:09 a.m. UTC | #1 
On Mon, Apr 01, 2019 at 11:00:06PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This defines the color lut ranges for 10bit and multi
> segmented gamma range for ICL.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c | 301 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 297 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index f2907cf..84d93ec 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -1083,9 +1083,279 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>  	return 0;
>  }
>  
> +enum {
> +	I9XX_LUT_SIZE_8BIT = 256,
> +	I9XX_LUT_SIZE_10BIT = 129,
> +
> +	ILK_LUT_SIZE_10BIT = 1024,
> +	ILK_LUT_SIZE_12BIT = 513,
> +
> +	IVB_LUT_SIZE_SPLIT = 512,
> +
> +	CHV_LUT_SIZE_CGM_DEGAMMA = 65,
> +	CHV_LUT_SIZE_CGM_GAMMA = 257,
> +};
> +
> +#define I9XX_GAMMA_8 \
> +	{ \
> +		.flags = DRM_MODE_LUT_GAMMA, \
> +		.count = 256, \
> +		.input_bpc = 8, .output_bpc = 8, \
> +		.start = 0, .end = (1 << 8) - 1, \
> +		.min = 0, .max = (1 << 8) - 1, \
> +	}
> +
> +static const struct drm_color_lut_range i9xx_gamma_8[] = {
> +	I9XX_GAMMA_8,
> +};
> +
> +static const struct drm_color_lut_range i9xx_gamma_10_slope[] = {
> +	{
> +		.flags = (DRM_MODE_LUT_GAMMA |
> +			  DRM_MODE_LUT_INTERPOLATE |
> +			  DRM_MODE_LUT_NON_DECREASING),
> +		.count = 129,
> +		.input_bpc = 10, .output_bpc = 10,
> +		.start = 0, .end = 1 << 10,
> +		.min = 0, .max = (1 << 10) - 1,
> +	},
> +};

Step 1 should probably be to advertise these for the gamma modes we
currently have, on every platform.
Shankar, Uma April 8, 2019, 12:28 p.m. UTC | #2 
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Monday, April 8, 2019 3:39 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Lankhorst,
>Maarten <maarten.lankhorst@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
>Sharma, Shashank <shashank.sharma@intel.com>; emil.l.velikov@gmail.com;
>brian.starkey@arm.com; dcastagna@chromium.org; seanpaul@chromium.org;
>harry.wentland@amd.com; Roper, Matthew D <matthew.d.roper@intel.com>
>Subject: Re: [v2 2/7] drm/i915: Define color lut range structure
>
>On Mon, Apr 01, 2019 at 11:00:06PM +0530, Uma Shankar wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> This defines the color lut ranges for 10bit and multi segmented gamma
>> range for ICL.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_color.c | 301
>> ++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 297 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index f2907cf..84d93ec 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -1083,9 +1083,279 @@ static int icl_color_check(struct intel_crtc_state
>*crtc_state)
>>  	return 0;
>>  }
>>
>> +enum {
>> +	I9XX_LUT_SIZE_8BIT = 256,
>> +	I9XX_LUT_SIZE_10BIT = 129,
>> +
>> +	ILK_LUT_SIZE_10BIT = 1024,
>> +	ILK_LUT_SIZE_12BIT = 513,
>> +
>> +	IVB_LUT_SIZE_SPLIT = 512,
>> +
>> +	CHV_LUT_SIZE_CGM_DEGAMMA = 65,
>> +	CHV_LUT_SIZE_CGM_GAMMA = 257,
>> +};
>> +
>> +#define I9XX_GAMMA_8 \
>> +	{ \
>> +		.flags = DRM_MODE_LUT_GAMMA, \
>> +		.count = 256, \
>> +		.input_bpc = 8, .output_bpc = 8, \
>> +		.start = 0, .end = (1 << 8) - 1, \
>> +		.min = 0, .max = (1 << 8) - 1, \
>> +	}
>> +
>> +static const struct drm_color_lut_range i9xx_gamma_8[] = {
>> +	I9XX_GAMMA_8,
>> +};
>> +
>> +static const struct drm_color_lut_range i9xx_gamma_10_slope[] = {
>> +	{
>> +		.flags = (DRM_MODE_LUT_GAMMA |
>> +			  DRM_MODE_LUT_INTERPOLATE |
>> +			  DRM_MODE_LUT_NON_DECREASING),
>> +		.count = 129,
>> +		.input_bpc = 10, .output_bpc = 10,
>> +		.start = 0, .end = 1 << 10,
>> +		.min = 0, .max = (1 << 10) - 1,
>> +	},
>> +};
>
>Step 1 should probably be to advertise these for the gamma modes we currently have,
>on every platform.

Ok, focussed here mainly on multi-segmented gamma. But will add all the gamma modes
supported on various platforms.

>--
>Ville Syrjälä
>Intel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index f2907cf..84d93ec 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1083,9 +1083,279 @@  static int icl_color_check(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+enum {
+	I9XX_LUT_SIZE_8BIT = 256,
+	I9XX_LUT_SIZE_10BIT = 129,
+
+	ILK_LUT_SIZE_10BIT = 1024,
+	ILK_LUT_SIZE_12BIT = 513,
+
+	IVB_LUT_SIZE_SPLIT = 512,
+
+	CHV_LUT_SIZE_CGM_DEGAMMA = 65,
+	CHV_LUT_SIZE_CGM_GAMMA = 257,
+};
+
+#define I9XX_GAMMA_8 \
+	{ \
+		.flags = DRM_MODE_LUT_GAMMA, \
+		.count = 256, \
+		.input_bpc = 8, .output_bpc = 8, \
+		.start = 0, .end = (1 << 8) - 1, \
+		.min = 0, .max = (1 << 8) - 1, \
+	}
+
+static const struct drm_color_lut_range i9xx_gamma_8[] = {
+	I9XX_GAMMA_8,
+};
+
+static const struct drm_color_lut_range i9xx_gamma_10_slope[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 129,
+		.input_bpc = 10, .output_bpc = 10,
+		.start = 0, .end = 1 << 10,
+		.min = 0, .max = (1 << 10) - 1,
+	},
+};
+
+#define I965_GAMMA_10 \
+	{ \
+		.flags = (DRM_MODE_LUT_GAMMA | \
+			  DRM_MODE_LUT_INTERPOLATE | \
+			  DRM_MODE_LUT_NON_DECREASING), \
+		.count = 128, \
+		.input_bpc = 10, .output_bpc = 16, \
+		.start = 0, .end = (1 << 10) - (1 << 10) / 128, \
+		.min = 0, .max = (1 << 16) - 1, \
+	}, \
+	/* PIPEGCMAX */ \
+	{ \
+		.flags = (DRM_MODE_LUT_GAMMA | \
+			  DRM_MODE_LUT_INTERPOLATE | \
+			  DRM_MODE_LUT_REUSE_LAST | \
+			  DRM_MODE_LUT_NON_DECREASING), \
+		.count = 1, \
+		.input_bpc = 10, .output_bpc = 16, \
+		.start = (1 << 10) - (1 << 10) / 128, .end = 1 << 10, \
+		.min = 0, .max = 1 << 16, \
+	}
+
+static const struct drm_color_lut_range i965_gamma_10[] = {
+	I965_GAMMA_10,
+};
+
+static const struct drm_color_lut_range ilk_gamma_degamma_8[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_DEGAMMA),
+		.count = 256,
+		.input_bpc = 8, .output_bpc = 8,
+		.start = 0, .end = (1 << 8) - 1,
+		.min = 0, .max = (1 << 8) - 1,
+	},
+};
+
+static const struct drm_color_lut_range ilk_gamma_degamma_10[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_DEGAMMA),
+		.count = 1024,
+		.input_bpc = 10, .output_bpc = 10,
+		.start = 0, .end = (1 << 10) - 1,
+		.min = 0, .max = (1 << 10) - 1,
+	},
+};
+
+static const struct drm_color_lut_range ilk_gamma_degamma_12p4[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_DEGAMMA |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 512,
+		.input_bpc = 12, .output_bpc = 16,
+		.start = 0, .end = (1 << 12) - (1 << 12) / 512,
+		.min = 0, .max = (1 << 16) - 1,
+	},
+	/* PIPEGCMAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_DEGAMMA |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 10, .output_bpc = 16,
+		.start = (1 << 12) - (1 << 12) / 512, .end = 1 << 12,
+		.min = 0, .max = 1 << 16,
+	},
+};
+
+static const struct drm_color_lut_range glk_gamma_10[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE),
+		.count = 1024,
+		.input_bpc = 10, .output_bpc = 10,
+		.start = 0, .end = (1 << 10) - 1,
+		.min = 0, .max = (1 << 10) - 1,
+	},
+	/* PAL_EXT_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 10, .output_bpc = 16,
+		.start = 1 << 10, .end = 3 << 10,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+	/* PAL_EXT2_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 10, .output_bpc = 16,
+		.start = 3 << 12, .end = 7 << 12,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+};
+
+/* FIXME input bpc? */
+static const struct drm_color_lut_range glk_gamma_12p4[] = {
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 512,
+		.input_bpc = 16, .output_bpc = 16,
+		.start = 0, .end = (1 << 16) - (1 << 16) / 512,
+		.min = 0, .max = (1 << 16) - 1,
+	},
+	/* PAL_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 16, .output_bpc = 16,
+		.start = (1 << 16) - (1 << 16) / 512, .end = 1 << 16,
+		.min = 0, .max = 1 << 16,
+	},
+	/* PAL_EXT_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 16, .output_bpc = 16,
+		.start = 1 << 16, .end = 3 << 16,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+	/* PAL_EXT2_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 16, .output_bpc = 16,
+		.start = 3 << 16, .end = 7 << 16,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+};
+
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range icl_multi_seg_gamma[] = {
+	/* segment 1 aka. super fine segment */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 9,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 0, .end = (1 << 24) / (128 * 256),
+		.min = 0, .max = (1 << 16) - 1,
+	},
+	/* segment 2 aka. fine segment */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 257,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 0, .end = (1 << 24) / 128,
+		.min = 0, .max = (1 << 16) - 1,
+	},
+	/* segment 3 aka. coarse segment */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 257,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 0, .end = (1 << 24) - (1 << 24) / 256,
+		.min = 0, .max = (1 << 16) - 1,
+	},
+	/* segment 3 aka. coarse segment / PAL_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = (1 << 24) - (1 << 24) / 256, .end = 1 << 24,
+		.min = 0, .max = 1 << 16,
+	},
+	/* PAL_EXT_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 1 << 24, .end = 3 << 24,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+	/* PAL_EXT2_GC_MAX */
+	{
+		.flags = (DRM_MODE_LUT_GAMMA |
+			  DRM_MODE_LUT_REFLECT_NEGATIVE |
+			  DRM_MODE_LUT_INTERPOLATE |
+			  DRM_MODE_LUT_REUSE_LAST |
+			  DRM_MODE_LUT_NON_DECREASING),
+		.count = 1,
+		.input_bpc = 24, .output_bpc = 16,
+		.start = 3 << 24, .end = 7 << 24,
+		.min = 0, .max = (8 << 16) - 1,
+	},
+};
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int degamma_lut_size, gamma_lut_size;
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
@@ -1100,14 +1370,37 @@  void intel_color_init(struct intel_crtc *crtc)
 			dev_priv->display.load_luts = i9xx_load_luts;
 		}
 	} else {
-		if (INTEL_GEN(dev_priv) >= 11)
+		if (INTEL_GEN(dev_priv) >= 11) {
 			dev_priv->display.color_check = icl_color_check;
-		else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+
+			/* don't advertize the >= 1.0 entries */
+			degamma_lut_size = 0;
+			gamma_lut_size = ILK_LUT_SIZE_10BIT;
+
+			drm_color_add_gamma_mode_range(&dev_priv->drm,
+						       "8bit gamma",
+						       i9xx_gamma_8,
+						       sizeof(i9xx_gamma_8));
+			drm_color_add_gamma_mode_range(&dev_priv->drm,
+						       "10bit gamma",
+							glk_gamma_10,
+							sizeof(glk_gamma_10));
+			drm_color_add_gamma_mode_range(&dev_priv->drm,
+						       "interpolated gamma",
+							glk_gamma_12p4,
+							sizeof(glk_gamma_12p4));
+			drm_color_add_gamma_mode_range(&dev_priv->drm,
+						       "multi-segmented gamma",
+							icl_multi_seg_gamma,
+							sizeof(icl_multi_seg_gamma));
+		} else if (INTEL_GEN(dev_priv) >= 10 ||
+			   IS_GEMINILAKE(dev_priv)) {
 			dev_priv->display.color_check = glk_color_check;
-		else if (INTEL_GEN(dev_priv) >= 8)
+		} else if (INTEL_GEN(dev_priv) >= 8) {
 			dev_priv->display.color_check = bdw_color_check;
-		else
+		} else {
 			dev_priv->display.color_check = ilk_color_check;
+		}
 
 		if (INTEL_GEN(dev_priv) >= 9)
 			dev_priv->display.color_commit = skl_color_commit;