| Message ID | 1581481604-24499-2-git-send-email-yamonkar@cadence.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper. | expand |
On 12/02/2020 06:26, Yuti Amonkar wrote: > Document the bindings used for the Cadence MHDP DPI/DP bridge in > yaml format. > > Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../bindings/display/bridge/cdns,mhdp.yaml | 125 ++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > new file mode 100644 > index 000000000000..e7f84ed1d2da > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > @@ -0,0 +1,125 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence MHDP bridge > + > +maintainers: > + - Swapnil Jakhade <sjakhade@cadence.com> > + - Yuti Amonkar <yamonkar@cadence.com> > + > +properties: > + compatible: > + enum: > + - cdns,mhdp8546 > + - ti,j721e-mhdp8546 > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: > + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). "up to". Add space before (. > + The AUX and PMA registers are mapped to associated phy driver. > + - description: > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > + > + reg-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: mhdptx > + - const: j721e-intg > + > + clocks: > + maxItems: 1 > + description: > + DP bridge clock, it's used by the IP to know how to translate a number of > + clock cycles into a time (which is used to comply with DP standard timings > + and delays). > + > + phys: > + description: Phandle to the DisplyPort phy. "Display" Tomi
Hi Yuti, Thank you for the patch. On Thu, Feb 13, 2020 at 11:16:51AM +0200, Tomi Valkeinen wrote: > On 12/02/2020 06:26, Yuti Amonkar wrote: > > Document the bindings used for the Cadence MHDP DPI/DP bridge in > > yaml format. > > > > Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > .../bindings/display/bridge/cdns,mhdp.yaml | 125 ++++++++++++++++++ > > 1 file changed, 125 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > new file mode 100644 > > index 000000000000..e7f84ed1d2da > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > @@ -0,0 +1,125 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Cadence MHDP bridge > > + > > +maintainers: > > + - Swapnil Jakhade <sjakhade@cadence.com> > > + - Yuti Amonkar <yamonkar@cadence.com> > > + > > +properties: > > + compatible: > > + enum: > > + - cdns,mhdp8546 > > + - ti,j721e-mhdp8546 > > + > > + reg: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - description: > > + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). > > "up to". Add space before (. > > > + The AUX and PMA registers are mapped to associated phy driver. I wouldn't mention driver here, as that's a software concept unrelated to DT bindings. You could write "The AUX and PMA registers are not part of this range, they are instead included in the associated PHY.". > > + - description: > > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > > + > > + reg-names: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - const: mhdptx > > + - const: j721e-intg > > + > > + clocks: > > + maxItems: 1 > > + description: > > + DP bridge clock, it's used by the IP to know how to translate a number of s/it's // > > + clock cycles into a time (which is used to comply with DP standard timings > > + and delays). > > + > > + phys: > > + description: Phandle to the DisplyPort phy. > > "Display" And s/Phandle/phandle/, and s/phy/PHY/. Shouldn't this bridge also have port nodes ?
Hi Yuti, On Sun, Feb 16, 2020 at 05:28:40PM +0200, Laurent Pinchart wrote: > On Thu, Feb 13, 2020 at 11:16:51AM +0200, Tomi Valkeinen wrote: > > On 12/02/2020 06:26, Yuti Amonkar wrote: > > > Document the bindings used for the Cadence MHDP DPI/DP bridge in > > > yaml format. > > > > > > Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > --- > > > .../bindings/display/bridge/cdns,mhdp.yaml | 125 ++++++++++++++++++ > > > 1 file changed, 125 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > > new file mode 100644 > > > index 000000000000..e7f84ed1d2da > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > > @@ -0,0 +1,125 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > + > > > +title: Cadence MHDP bridge > > > + > > > +maintainers: > > > + - Swapnil Jakhade <sjakhade@cadence.com> > > > + - Yuti Amonkar <yamonkar@cadence.com> > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - cdns,mhdp8546 > > > + - ti,j721e-mhdp8546 > > > + > > > + reg: > > > + minItems: 1 > > > + maxItems: 2 > > > + items: > > > + - description: > > > + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). > > > > "up to". Add space before (. > > > > > + The AUX and PMA registers are mapped to associated phy driver. > > I wouldn't mention driver here, as that's a software concept unrelated > to DT bindings. You could write "The AUX and PMA registers are not part > of this range, they are instead included in the associated PHY.". > > > > + - description: > > > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > > > + > > > + reg-names: > > > + minItems: 1 > > > + maxItems: 2 > > > + items: > > > + - const: mhdptx > > > + - const: j721e-intg > > > + > > > + clocks: > > > + maxItems: 1 > > > + description: > > > + DP bridge clock, it's used by the IP to know how to translate a number of > > s/it's // > > > > + clock cycles into a time (which is used to comply with DP standard timings > > > + and delays). > > > + > > > + phys: > > > + description: Phandle to the DisplyPort phy. > > > > "Display" > > And s/Phandle/phandle/, and s/phy/PHY/. > > Shouldn't this bridge also have port nodes ? Oops, sorry, I missed that Tomi's reply has removed part of the original patch. Please disregard this last comment, I'll reply to the original.
Hi Yuti, Thank you for the patch. On Wed, Feb 12, 2020 at 05:26:42AM +0100, Yuti Amonkar wrote: > Document the bindings used for the Cadence MHDP DPI/DP bridge in > yaml format. > > Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../bindings/display/bridge/cdns,mhdp.yaml | 125 ++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > new file mode 100644 > index 000000000000..e7f84ed1d2da > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > @@ -0,0 +1,125 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence MHDP bridge > + > +maintainers: > + - Swapnil Jakhade <sjakhade@cadence.com> > + - Yuti Amonkar <yamonkar@cadence.com> > + > +properties: > + compatible: > + enum: > + - cdns,mhdp8546 > + - ti,j721e-mhdp8546 > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: > + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). > + The AUX and PMA registers are mapped to associated phy driver. > + - description: > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > + > + reg-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: mhdptx > + - const: j721e-intg > + > + clocks: > + maxItems: 1 > + description: > + DP bridge clock, it's used by the IP to know how to translate a number of > + clock cycles into a time (which is used to comply with DP standard timings > + and delays). > + > + phys: > + description: Phandle to the DisplyPort phy. > + > + ports: > + type: object > + description: > + Ports as described in Documentation/devicetree/bindings/graph.txt > + > + properties: > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + port@0: > + type: object > + description: > + input port representing the DP bridge input s/input port/Input port/ and s/bridge input/bridge input./ > + > + port@1: > + type: object > + description: > + output port representing the DP bridge output. s/output port/Output port/ > + > + required: > + - port@0 > + - port@1 > + - '#address-cells' > + - '#size-cells' > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: ti,j721e-mhdp8546 > + then: > + properties: > + reg: > + minItems: 2 > + reg-names: > + minItems: 2 > + > +required: > + - compatible > + - clocks > + - reg > + - reg-names > + - phys > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + mhdp: dp-bridge@f0fb000000 { > + compatible = "cdns,mhdp8546"; > + reg = <0xf0 0xfb000000 0x0 0x1000000>; > + reg-names = "mhdptx"; > + clocks = <&mhdp_clock>; > + phys = <&dp_phy>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dp_bridge_input: endpoint { > + remote-endpoint = <&xxx_dpi_output>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dp_bridge_output: endpoint { > + remote-endpoint = <&xxx_dp_connector_input>; > + }; > + }; > + }; > + }; > +... Really good bindings ! With the above comments addressed, as well as he one in reply to Tomi's review, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml new file mode 100644 index 000000000000..e7f84ed1d2da --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence MHDP bridge + +maintainers: + - Swapnil Jakhade <sjakhade@cadence.com> + - Yuti Amonkar <yamonkar@cadence.com> + +properties: + compatible: + enum: + - cdns,mhdp8546 + - ti,j721e-mhdp8546 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). + The AUX and PMA registers are mapped to associated phy driver. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: mhdptx + - const: j721e-intg + + clocks: + maxItems: 1 + description: + DP bridge clock, it's used by the IP to know how to translate a number of + clock cycles into a time (which is used to comply with DP standard timings + and delays). + + phys: + description: Phandle to the DisplyPort phy. + + ports: + type: object + description: + Ports as described in Documentation/devicetree/bindings/graph.txt + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: + input port representing the DP bridge input + + port@1: + type: object + description: + output port representing the DP bridge output. + + required: + - port@0 + - port@1 + - '#address-cells' + - '#size-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: ti,j721e-mhdp8546 + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + +required: + - compatible + - clocks + - reg + - reg-names + - phys + - ports + +additionalProperties: false + +examples: + - | + mhdp: dp-bridge@f0fb000000 { + compatible = "cdns,mhdp8546"; + reg = <0xf0 0xfb000000 0x0 0x1000000>; + reg-names = "mhdptx"; + clocks = <&mhdp_clock>; + phys = <&dp_phy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_bridge_input: endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + + port@1 { + reg = <1>; + dp_bridge_output: endpoint { + remote-endpoint = <&xxx_dp_connector_input>; + }; + }; + }; + }; +...