From patchwork Wed May 27 07:27:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11574949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4B9E13B4 for ; Thu, 28 May 2020 07:44:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2F7521475 for ; Thu, 28 May 2020 07:44:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="j/De+h+Q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2F7521475 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6968A6E40D; Thu, 28 May 2020 07:43:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D641898CA for ; Wed, 27 May 2020 07:28:07 +0000 (UTC) Received: by mail-pf1-x442.google.com with SMTP id v63so11447947pfb.10 for ; Wed, 27 May 2020 00:28:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PnARTlRhVkBUQkPqC454r4YU05zMHZz2LfM1l53WRb0=; b=j/De+h+QmNQ49bidmH96zLrOu2OBXrIIB6Y9QUEalQjZ1catzyle70SRBwOcwMWe+z iZIt54zFlbJqY6v33AGBhOtUxRV6Szu1l68EY9j0+rctjO15uFYPrWRUy3ghFb1xW7/H abClqYr3/WLdGWazduydiccGKMYgnyX/8lNoQoRJwJbpCE62LWArAo1EIY7SkaA1x3Hy nzV7QCUDYFaESm+gzjKIQGUvU0Na2CtsCyVwB+tlMQSf8mPIG7N0fY14a/SFd+dOWhAt 0otXEMgwfJZ4aADjlvQwy4zZJ3PleE0M9x94oSgoEBNHkCtYi9ZFIcjq5FV59Ysyeooz E3Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PnARTlRhVkBUQkPqC454r4YU05zMHZz2LfM1l53WRb0=; b=iUYXnSg7yLOcXzB02OKxIK5XWRRbE9Cf55O9UVVmG6EOS/cB//mq6N6NgoMENB8yTF i9o6f7BtEZCl1GucYZrbYBRgtLn5Yf/v4419pLAAapiVevnMuFnUW8pDGdEMitU6ZQtn tNgqkCM0riJpxxVN7bikm7QVnp/6OykBnPWkTbyT8iCssRfCCBjO4rXPRAxbFlTSt0Ml mPCLLU1yqrdOKvfP7xBByKtFsikZ5tgPLZmKsJH5mNRlh9G4msqt8skkwS+OKp+0Q8cd 1Xb/9xxYeTGROSefVdOoO3ecIBSw8M3UI0/NXCA/3rFXwftiyuuzVZMK2bKvxnREeDp5 aKpQ== X-Gm-Message-State: AOAM5336nJ2UklR7k5gZkSaOvGSKfswkY0M0sIldmBbmf6tj+nT7oBmr JlQSfQwZ7gF7GuTaQWNK+H4= X-Google-Smtp-Source: ABdhPJx3SUGNW2XD8h8US9uScxTycxVHXeqpLbmx7fMrRID3k4oOipLAcBnlwkA/Q3ap+M2eKxw16w== X-Received: by 2002:aa7:9ab6:: with SMTP id x22mr2661695pfi.136.1590564486694; Wed, 27 May 2020 00:28:06 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.191.44]) by smtp.gmail.com with ESMTPSA id q201sm1371842pfq.40.2020.05.27.00.28.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 May 2020 00:28:06 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org, andy.shevchenko@gmail.com, noralf@tronnes.org, linus.walleij@linaro.org, broonie@kernel.org Subject: [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate Date: Wed, 27 May 2020 15:27:29 +0800 Message-Id: <1590564453-24499-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com> References: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 28 May 2020 07:43:50 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, dillonhua@gmail.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, dillon min , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: dillon min This is due to misuse ‘PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in include/dt-bindings/clock/stm32fx-clock.h). 'post_div' point to 'post_div_data[]', 'post_div->pll_num' is PLL_I2S or PLL_SAI. 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return from stm32f4_rcc_register_pll() but, at line 1777 of driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]', equal to 'clks[PLL_SAI]', this is invalid array member at that time. Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs") Signed-off-by: dillon min --- Hi Stephen Boyd, This update include below changes since V5 1 separate '[PATCH v5 5/8]' patch to two submits 2 each one has a Fixes tags best regards. drivers/clk/clk-stm32f4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 18117ce5ff85..42ca2dd86aea 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = { #define MAX_POST_DIV 3 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, };