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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR0402MB3952.eurprd04.prod.outlook.com (2603:10a6:803:1c::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12; Fri, 11 Dec 2020 01:55:00 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3632.023; Fri, 11 Dec 2020 01:55:00 +0000 From: Liu Ying To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/5] dt-bindings: phy: Convert mixel, mipi-dsi-phy to json-schema Date: Fri, 11 Dec 2020 09:46:20 +0800 Message-Id: <1607651182-12307-4-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> References: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3676.5 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?sEjiKTa8Bwtc6bgSiUyKR01PDOftks?= =?utf-8?q?KsBMhc64VueCqVlc5m6JXt1kf6tr09JQQ7iA1m77uZ3b647cyc8DpeoK0++FfQsJ4?= =?utf-8?q?6lv75sPSAMK/WZyTqRxk2qlEPv/d0/UWTEI22SGtyMuCNbN26uzgmyBAUrxgkZ0oG?= =?utf-8?q?PV7v0A9APgd89frC/BRKtexM1vrOLwNkSURv+KI0yauJGq55gX9Yu0Bw3wW2+gh+x?= =?utf-8?q?w/zlleaAc9lxrwQyTj67sAD0QRzGCIqVFHj614tA58TUECligY6lToH4FyHvbsleT?= =?utf-8?q?whMukngAZEkBmc+a+JE0RQf9ySNLFnqprRo5vzEwFy3zdKng7KpmZRkqk4RlxB96G?= =?utf-8?q?sfFODiYf+r8dUzDLfpR0f+y1Ql2tMmkwcEQxfcjd5aP+zRQEG3sG77SABzOy3TFDB?= =?utf-8?q?GeOM2jFTXXkji67a60kQxVe7xUawnD9FWyZIdQ+IibDJFjsPe0jrp089bjIQAchMI?= =?utf-8?q?YV7QaPMtWHymtaO2jV7Jcbw5Sqc/g0jatHFfA2W+koiAxszlzoWbaJTfV9DG1Be5I?= =?utf-8?q?kmz0o0Ec0DBfgt/DpbPwXtLdB74hDh6hDXUdB8Njsefgx43ns4rvia3edhfsRXabT?= =?utf-8?q?8RVHv8vbvt0pDDUedUlUZv4fyAe4C5jSvipeRw1hdq91ZtkRJxRNIrUC4zG7OJTOM?= =?utf-8?q?cw3QnXuDNtA/8n7q2dzCfypmqa/Lno3L+zjk9t3zRgYcjRsQpmXYgoJ91JlcGLKlw?= =?utf-8?q?iS3eOH33BQGWpwu4XTQqHvvr/FG12tO186el1gfQRcy5LUeITguof8q+FyPcMg4mn?= =?utf-8?q?gabiAJNixT4nwPypmZ6imDGmSFshcGy19hhPXkhJ9f02meViGetUnAaHCHGw8Mn1O?= =?utf-8?q?ctD2kystActc5JXkYnHVmRkKK3DUKoNoUUrxsoHrycLY9TK8f+jEq/yclsyUd5k3b?= =?utf-8?q?izhxKYuGk/tJZA97JRAaS04AxC2X4lqZQZS+EB/VtgjUhPmRq2/83tZXoh8+a4xMj?= =?utf-8?q?0hwFMNGW4K5Ixl1tWCG?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2020 01:55:00.2885 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: 37b54dbb-0972-4232-5a68-08d89d77c4f8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Xr1zB7tatXcVZIsVsDzWPvJ17BHqe/GpkUeYAQVaQCFpd2WLdjby0z8s7ENxPAAv770PNsQQ0qJTbswgD58ahA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3952 X-Mailman-Approved-At: Fri, 11 Dec 2020 08:16:08 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: martin.kepplinger@puri.sm, jernej.skrabec@siol.net, kernel@pengutronix.de, narmstrong@baylibre.com, airlied@linux.ie, s.hauer@pengutronix.de, jonas@kwiboo.se, kishon@ti.com, a.hajda@samsung.com, vkoul@kernel.org, robh+dt@kernel.org, Laurent.pinchart@ideasonboard.com, robert.chiras@nxp.com, shawnguo@kernel.org, agx@sigxcpu.org, linux-imx@nxp.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patch converts the mixel,mipi-dsi-phy binding to DT schema format using json-schema. Comparing to the plain text version, the new binding adds the 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' properites, otherwise 'make dtbs_check' would complain that there are mis-matches. Also, the new binding requires the 'power-domains' property since all potential SoCs that embed this PHY would provide a power domain for it. The example of the new binding takes reference to the latest dphy node in imx8mq.dtsi. Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Signed-off-by: Liu Ying Reviewed-by: Rob Herring Reviewed-by: Guido Günther --- v2->v3: * Improve the 'clock-names' property by dropping 'items:'. v1->v2: * Newly introduced in v2. (Guido) .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --------- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 72 ++++++++++++++++++++++ 2 files changed, 72 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt deleted file mode 100644 index 9b23407..00000000 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt +++ /dev/null @@ -1,29 +0,0 @@ -Mixel DSI PHY for i.MX8 - -The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the -MIPI-DSI IP from Northwest Logic). It represents the physical layer for the -electrical signals for DSI. - -Required properties: -- compatible: Must be: - - "fsl,imx8mq-mipi-dphy" -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "phy_ref": phandle and specifier referring to the DPHY ref clock -- reg: the register range of the PHY controller -- #phy-cells: number of cells in PHY, as defined in - Documentation/devicetree/bindings/phy/phy-bindings.txt - this must be <0> - -Optional properties: -- power-domains: phandle to power domain - -Example: - dphy: dphy@30a0030 { - compatible = "fsl,imx8mq-mipi-dphy"; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - reg = <0x30a00300 0x100>; - power-domains = <&pd_mipi0>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml new file mode 100644 index 00000000..c34f2e6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel DSI PHY for i.MX8 + +maintainers: + - Guido Günther + +description: | + The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the + MIPI-DSI IP from Northwest Logic). It represents the physical layer for the + electrical signals for DSI. + +properties: + compatible: + enum: + - fsl,imx8mq-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: phy_ref + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include + dphy: dphy@30a0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + reg = <0x30a00300 0x100>; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&pgc_mipi>; + };