From patchwork Sat Dec 12 04:11:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 11971487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 255F7C4361B for ; Mon, 14 Dec 2020 08:18:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CAB07207A5 for ; Mon, 14 Dec 2020 08:18:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CAB07207A5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E76ED6E0A8; Mon, 14 Dec 2020 08:17:45 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTP id 553426E56A for ; Sat, 12 Dec 2020 04:12:06 +0000 (UTC) X-UUID: 6348c67c76b34711b50e75b435d8ee71-20201212 X-UUID: 6348c67c76b34711b50e75b435d8ee71-20201212 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1551359386; Sat, 12 Dec 2020 12:12:03 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 12 Dec 2020 12:12:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 12 Dec 2020 12:12:01 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger Subject: [PATCH v2, 02/17] dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for mt8192 display Date: Sat, 12 Dec 2020 12:11:42 +0800 Message-ID: <1607746317-4696-3-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1607746317-4696-1-git-send-email-yongqiang.niu@mediatek.com> References: <1607746317-4696-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Mon, 14 Dec 2020 08:17:40 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add CLK_MM_DISP_CONFIG control description for mt8192 displa Signed-off-by: Yongqiang Niu --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 1972fa7..dfbec76 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -54,6 +54,9 @@ Required properties (all function blocks): DPI controller nodes have multiple clock inputs. These are documented in mediatek,dsi.txt and mediatek,dpi.txt, respectively. An exception is that the mt8183 mutex is always free running with no clocks property. + An exception is that the mt8192 display add 2 more clocks(CLK_MM_DISP_CONFIG, CLK_MM_26MHZ), + and these 2 clocks need enabled before display module work like mutex clock, so we add these + 2 clocks controled same with mutex clock. Required properties (DMA function blocks): - compatible: Should be one of