| Message ID | 1645133788-5057-2-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm/dpu: enable widebus feature base on chip hardware revision | expand |
On Fri, 18 Feb 2022 at 00:36, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote: > > The “DP timing” requires the active region to be defined in the > bottom-right corner of the frame dimensions which is different > with DSI. Therefore both display_h_end and display_v_end need > to be adjusted accordingly. However current implementation has > only display_h_end adjusted. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Fixes: fc3a69ec68d3 ("drm/msm/dpu: intf timing path for displayport") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 116e2b5..284f561 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -148,6 +148,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > active_v_end = active_v_start + (p->yres * hsync_period) - 1; > > display_v_start += p->hsync_pulse_width + p->h_back_porch; > + display_v_end -= p->h_front_porch; > > active_hctl = (active_h_end << 16) | active_h_start; > display_hctl = active_hctl; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
Quoting Kuogee Hsieh (2022-02-17 13:36:25) > The “DP timing” requires the active region to be defined in the > bottom-right corner of the frame dimensions which is different > with DSI. Therefore both display_h_end and display_v_end need > to be adjusted accordingly. However current implementation has > only display_h_end adjusted. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- Is this not a problem for me because this is set already to something correct in the hardware? Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On 2/18/2022 6:48 PM, Stephen Boyd wrote: > Quoting Kuogee Hsieh (2022-02-17 13:36:25) >> The “DP timing” requires the active region to be defined in the >> bottom-right corner of the frame dimensions which is different >> with DSI. Therefore both display_h_end and display_v_end need >> to be adjusted accordingly. However current implementation has >> only display_h_end adjusted. >> >> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >> --- > Is this not a problem for me because this is set already to something > correct in the hardware? There will have some pixels step into front porch area. It should not cause any visual problem. > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 116e2b5..284f561 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -148,6 +148,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, active_v_end = active_v_start + (p->yres * hsync_period) - 1; display_v_start += p->hsync_pulse_width + p->h_back_porch; + display_v_end -= p->h_front_porch; active_hctl = (active_h_end << 16) | active_h_start; display_hctl = active_hctl;
The “DP timing” requires the active region to be defined in the bottom-right corner of the frame dimensions which is different with DSI. Therefore both display_h_end and display_v_end need to be adjusted accordingly. However current implementation has only display_h_end adjusted. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 + 1 file changed, 1 insertion(+)