| Message ID | 1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update mdp clk to max supported value to support higher refresh rates | expand |
On Mon, 14 Mar 2022 at 17:47, Vinod Polimera <quic_vpolimer@quicinc.com> wrote: > > use max clock during probe/bind sequence from the opp table. > The clock will be scaled down when framework sends an update. > > Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support") > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index e29796c..9c346ce 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1202,7 +1202,9 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) > struct platform_device *pdev = to_platform_device(dev); > struct drm_device *ddev = priv->dev; > struct dpu_kms *dpu_kms; > + struct dev_pm_opp *opp; > int ret = 0; > + unsigned long max_freq = ULONG_MAX; > > dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); > if (!dpu_kms) > @@ -1225,6 +1227,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) > } > dpu_kms->num_clocks = ret; > > + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); > + if (!IS_ERR(opp)) > + dev_pm_opp_put(opp); > + > + dev_pm_opp_set_rate(dev, max_freq); > + > platform_set_drvdata(pdev, dpu_kms); > > ret = msm_kms_init(&dpu_kms->base, &kms_funcs); > -- > 2.7.4 >
Quoting Vinod Polimera (2022-03-14 07:46:53) > use max clock during probe/bind sequence from the opp table. > The clock will be scaled down when framework sends an update. Capitalize 'use'. Why is it important to use max frequency during probe/bind? Does not setting the clk rate during probe mean that we'll never use the max rate? Does it speed things up during probe?
Hi, On Mon, Mar 14, 2022 at 7:47 AM Vinod Polimera <quic_vpolimer@quicinc.com> wrote: > > use max clock during probe/bind sequence from the opp table. > The clock will be scaled down when framework sends an update. > > Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support") The "Fixes:" format is a little wrong. Should have more digits and a space before the parenthesis. AKA: Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ > 1 file changed, 8 insertions(+) This looks good to me now other than the bad Fixes tag. I presume you'll want to spin with the extra verbosity in the CL description that Stephen asked for, though. Reviewed-by: Douglas Anderson <dianders@chromium.org>
> -----Original Message----- > From: Stephen Boyd <swboyd@chromium.org> > Sent: Friday, March 18, 2022 2:41 AM > To: quic_vpolimer <quic_vpolimer@quicinc.com>; > devicetree@vger.kernel.org; dri-devel@lists.freedesktop.org; > freedreno@lists.freedesktop.org; linux-arm-msm@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; robdclark@gmail.com; > dmitry.baryshkov@linaro.org; dianders@chromium.org; quic_kalyant > <quic_kalyant@quicinc.com> > Subject: Re: [PATCH v6 1/5] drm/msm/disp/dpu1: set mdp clk to the > maximum frequency in opp table during probe > > WARNING: This email originated from outside of Qualcomm. Please be wary > of any links or attachments, and do not enable macros. > > Quoting Vinod Polimera (2022-03-14 07:46:53) > > use max clock during probe/bind sequence from the opp table. > > The clock will be scaled down when framework sends an update. > > Capitalize 'use'. > > Why is it important to use max frequency during probe/bind? Does not > setting the clk rate during probe mean that we'll never use the max > rate? Does it speed things up during probe? We need to vote mdp clock during probe/bind so that rails are not set at undetermined state as pointed out by Dmitry. Since we dont know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. Thanks, Vinod P.
On Mon, 21 Mar 2022 at 19:21, Vinod Polimera <vpolimer@qti.qualcomm.com> wrote: > > > > > -----Original Message----- > > From: Stephen Boyd <swboyd@chromium.org> > > Sent: Friday, March 18, 2022 2:41 AM > > To: quic_vpolimer <quic_vpolimer@quicinc.com>; > > devicetree@vger.kernel.org; dri-devel@lists.freedesktop.org; > > freedreno@lists.freedesktop.org; linux-arm-msm@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; robdclark@gmail.com; > > dmitry.baryshkov@linaro.org; dianders@chromium.org; quic_kalyant > > <quic_kalyant@quicinc.com> > > Subject: Re: [PATCH v6 1/5] drm/msm/disp/dpu1: set mdp clk to the > > maximum frequency in opp table during probe > > > > WARNING: This email originated from outside of Qualcomm. Please be wary > > of any links or attachments, and do not enable macros. > > > > Quoting Vinod Polimera (2022-03-14 07:46:53) > > > use max clock during probe/bind sequence from the opp table. > > > The clock will be scaled down when framework sends an update. > > > > Capitalize 'use'. > > > > Why is it important to use max frequency during probe/bind? Does not > > setting the clk rate during probe mean that we'll never use the max > > rate? Does it speed things up during probe? > > We need to vote mdp clock during probe/bind so that rails are not set at undetermined state as pointed out by Dmitry. > Since we dont know what will be the rate set in boot loader, it would be ideal to vote at max frequency. > There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. This should be expressed in the commit message.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e29796c..9c346ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1202,7 +1202,9 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) struct platform_device *pdev = to_platform_device(dev); struct drm_device *ddev = priv->dev; struct dpu_kms *dpu_kms; + struct dev_pm_opp *opp; int ret = 0; + unsigned long max_freq = ULONG_MAX; dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) @@ -1225,6 +1227,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) } dpu_kms->num_clocks = ret; + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + dev_pm_opp_set_rate(dev, max_freq); + platform_set_drvdata(pdev, dpu_kms); ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
use max clock during probe/bind sequence from the opp table. The clock will be scaled down when framework sends an update. Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 1 file changed, 8 insertions(+)