From patchwork Mon May 2 05:39:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 12833822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75FF9C433EF for ; Mon, 2 May 2022 05:39:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B29B710FEEC; Mon, 2 May 2022 05:39:54 +0000 (UTC) Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA0EF10FEEC; Mon, 2 May 2022 05:39:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651469993; x=1683005993; h=from:to:cc:subject:date:message-id:mime-version; bh=jb3pnIqkpNwqVcQECfW+8en2VGdWTFperQUr9rh8M8s=; b=HPkGCKGvD+bzJFPaEfvOQXFBbxbazW6EtRk74AR7On7sEe2MCyzy562K rrQVZprC+pv+lSiErAZarCn05rGsmpT0lDAlJPuM1PSKxsAMhCzyzzBMP tp7iiVkDeYAj61cZHlj4QaoJjhN30jTmqpvIvDwsCGDPFmkogdXqkxRMF U=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 01 May 2022 22:39:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2022 22:39:51 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 1 May 2022 22:39:50 -0700 Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 1 May 2022 22:39:50 -0700 From: Abhinav Kumar To: Subject: [PATCH] drm/msm/dpu: add missing break statement for update_pending_flush_wb() Date: Sun, 1 May 2022 22:39:41 -0700 Message-ID: <1651469981-21469-1-git-send-email-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abhinav Kumar , dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, dmitry.baryshkov@linaro.org, quic_jesszhan@quicinc.com, quic_aravindh@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add missing break statement for dpu_hw_ctl_update_pending_flush_wb(). Otherwise this leads to below build warning. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c:273:2: warning: unannotated fall-through between switch labels default: ^ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c:273:2: note: insert 'break;' to avoid fall-through default: ^ break; 1 warning generated. Fixes: 2e0086d8c61d ("drm/msm/dpu: add changes to support writeback in hw_ctl") Reported-by: kernel test robot Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 254fdf06bb42..c33e7ef611a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -270,6 +270,7 @@ static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx, case WB_1: case WB_2: ctx->pending_flush_mask |= BIT(WB_IDX); + break; default: break; }