diff mbox series

[RFC,1/3] drm/msm/dpu: add max external pixel clock for all targets

Message ID 1661830389-22439-2-git-send-email-quic_abhinavk@quicinc.com (mailing list archive)
State New, archived
Headers show
Series Limit pluggable display modes | expand

Commit Message

Abhinav Kumar Aug. 30, 2022, 3:33 a.m. UTC 
Add maximum external pixel clock for all targets based on
the advertised limits for each of them.

The pixel clock has been calculated from the timings mentioned
in the CEA specification for CEA modes and according to
the VESA CVT standard for the others.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
 2 files changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029fdc682..b04d219ac380 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -277,6 +277,7 @@  static const struct dpu_caps msm8998_dpu_caps = {
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 	.max_vdeci_exp = MAX_VERT_DECIMATION,
+	.max_ext_pclk = 594000,
 };
 
 static const struct dpu_caps qcm2290_dpu_caps = {
@@ -288,6 +289,7 @@  static const struct dpu_caps qcm2290_dpu_caps = {
 	.has_idle_pc = true,
 	.max_linewidth = 2160,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+	.max_ext_pclk = 101250,
 };
 
 static const struct dpu_caps sdm845_dpu_caps = {
@@ -304,6 +306,7 @@  static const struct dpu_caps sdm845_dpu_caps = {
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 	.max_vdeci_exp = MAX_VERT_DECIMATION,
+	.max_ext_pclk = 594000,
 };
 
 static const struct dpu_caps sc7180_dpu_caps = {
@@ -316,6 +319,7 @@  static const struct dpu_caps sc7180_dpu_caps = {
 	.has_idle_pc = true,
 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+	.max_ext_pclk = 312250,
 };
 
 static const struct dpu_caps sm8150_dpu_caps = {
@@ -332,6 +336,7 @@  static const struct dpu_caps sm8150_dpu_caps = {
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 	.max_vdeci_exp = MAX_VERT_DECIMATION,
+	.max_ext_pclk = 594000,
 };
 
 static const struct dpu_caps sc8180x_dpu_caps = {
@@ -348,6 +353,7 @@  static const struct dpu_caps sc8180x_dpu_caps = {
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 	.max_vdeci_exp = MAX_VERT_DECIMATION,
+	.max_ext_pclk = 594000,
 };
 
 static const struct dpu_caps sm8250_dpu_caps = {
@@ -362,6 +368,7 @@  static const struct dpu_caps sm8250_dpu_caps = {
 	.has_3d_merge = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+	.max_ext_pclk = 594000,
 };
 
 static const struct dpu_caps sc7280_dpu_caps = {
@@ -374,6 +381,7 @@  static const struct dpu_caps sc7280_dpu_caps = {
 	.has_idle_pc = true,
 	.max_linewidth = 2400,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+	.max_ext_pclk = 312250,
 };
 
 static const struct dpu_mdp_cfg msm8998_mdp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38ab1568..35cab76d9530 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -370,6 +370,7 @@  struct dpu_rotation_cfg {
 
 /**
  * struct dpu_caps - define DPU capabilities
+ * @max_ext_pclk       max pixel clock of the external display
  * @max_mixer_width    max layer mixer line width support.
  * @max_mixer_blendstages max layer mixer blend stages or
  *                       supported z order
@@ -386,6 +387,7 @@  struct dpu_rotation_cfg {
  * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
  */
 struct dpu_caps {
+	int max_ext_pclk;
 	u32 max_mixer_width;
 	u32 max_mixer_blendstages;
 	u32 qseed_type;