From patchwork Mon Dec 5 19:14:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 13065009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BFE1C63708 for ; Mon, 5 Dec 2022 19:15:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1EE710E284; Mon, 5 Dec 2022 19:15:04 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id E382710E11C; Mon, 5 Dec 2022 19:14:54 +0000 (UTC) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B5IQBS8004854; Mon, 5 Dec 2022 19:14:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=BqvH1ztPAkld+QNaf9LMrfSPdVr+UJRpC3ItvXdIn6s=; b=GFk564ONa9EW8hzGqaA2fTrniEKAVJTomR8o0Qe6xNG+5TOO52N91sK4gDU8+Gfdk/Km 4YKBIhfkF0rM/+FAQCi+J2M6x8QPipDotfBaKo+EhcGV5YHiBnf4MiDlHNvPuLHA2H+a K1ZwirdVXHIKmlv8tZndoDR2hHoTLLpls00jmvoKGQa3mZYUYojbpMp28O73E6FdfxYw fLOt5qY+zX5Q7Nlbp0oKw3T0JljdTC6dt3c8mAl8NmGAF59nTgV83q4oZ1RrHIeyc/t9 ns4ejqcFPhNZkZy0Wg1J5B9ht6NWZ9ZhfDSowGxwD2Cg6CqjLASitUApmADXa1oHZW8F 7Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3m7ymt500w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Dec 2022 19:14:49 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B5JEmMJ020402 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 5 Dec 2022 19:14:48 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 5 Dec 2022 11:14:47 -0800 From: Kuogee Hsieh To: , , , , , , , , , , , , , , , Subject: [PATCH v8 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint Date: Mon, 5 Dec 2022 11:14:29 -0800 Message-ID: <1670267670-15832-5-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1670267670-15832-1-git-send-email-quic_khsieh@quicinc.com> References: <1670267670-15832-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VPX6WWZU46rMufwvt6SBlqFhjHFG6xaY X-Proofpoint-GUID: VPX6WWZU46rMufwvt6SBlqFhjHFG6xaY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-05_01,2022-12-05_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212050160 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, Kuogee Hsieh , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add capability to parser and retrieve max DP link supported rate from link-frequencies property of dp_out endpoint. Changes in v6: -- second patch after split parser patch into two patches Changes in v7: -- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/dp/dp_parser.c | 19 +++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index b5f7e70..037dad8 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) static int dp_parser_misc(struct dp_parser *parser) { struct device_node *of_node = parser->pdev->dev.of_node; + struct device_node *endpoint; + u64 frequency; int cnt; /* * data-lanes is the property of dp_out endpoint */ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES); - if (cnt > 0) + if (cnt > 0) { parser->max_dp_lanes = cnt; - else { + + endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ + cnt = of_property_count_u64_elems(endpoint, "link-frequencies"); + if (cnt > 0) { + of_property_read_u64_index(endpoint, "link-frequencies", + cnt - 1, &frequency); + frequency /= 10; /* from symbol rate to link rate */ + parser->max_dp_link_rate = (frequency / 1000); /* kbits */ + } else { + parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */ + } + } else { /* * legacy code, data-lanes is the property of mdss_dp node */ @@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser) parser->max_dp_lanes = cnt; else parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ + + parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */ } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 866c1a8..3ddf639 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -15,6 +15,7 @@ #define DP_LABEL "MDSS DP DISPLAY" #define DP_MAX_PIXEL_CLK_KHZ 675000 #define DP_MAX_NUM_DP_LANES 4 +#define DP_LINK_RATE_HBR2 540000 enum dp_pm_type { DP_CORE_PM, @@ -119,6 +120,7 @@ struct dp_parser { struct dp_io io; struct dp_display_data disp_data; u32 max_dp_lanes; + u32 max_dp_link_rate; struct drm_bridge *next_bridge; int (*parse)(struct dp_parser *parser);