From patchwork Tue Dec 13 22:56:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 13072535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03A9EC4332F for ; Tue, 13 Dec 2022 22:57:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0AA510E382; Tue, 13 Dec 2022 22:57:15 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3332410E372; Tue, 13 Dec 2022 22:56:49 +0000 (UTC) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BDMQZRS014260; Tue, 13 Dec 2022 22:56:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=WkAJ2SZyaHUbH9fFpqfbaYKvKWX5dlJ6xd3Kje9WbaM=; b=hNCqZK/f5t4S1Nr/5jz0kYQlC0O8hnJxgFxn8hRaRyAsyLprBP4GjfLOCkIobDWI/Kxd PeirWKIbIsxFCFNEi6uFHi+S7SxNusYqt41KkimrH1lsQpTHHXfjKP5u12eCOb30/2Vh pSb0rkvFUKzRSlqUiwpdntyBeO5AHY/9HRdkpJHmi4ySjlDDGBM3RK8VXon+3O209man IpkxJVc4EpMLWwrumvVuufoQtNILA3H0nx/Jt/qDGyfhNUVatZbSKAiF7Zh0zgVXXHzH wptB8AZqr8sbD3Q0D13aePNC3mnEMkuCiSO/HLkPJAlzynZ2x9qTIwn21J4biPaVVd9D ZA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3meyf2rfh0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 22:56:44 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BDMuhJ2009163 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 22:56:43 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 13 Dec 2022 14:56:42 -0800 From: Kuogee Hsieh To: , , , , , , , , , , , , , , Subject: [PATCH v13 5/5] drm/msm/dp: add support of max dp link rate Date: Tue, 13 Dec 2022 14:56:21 -0800 Message-ID: <1670972181-4961-6-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1670972181-4961-1-git-send-email-quic_khsieh@quicinc.com> References: <1670972181-4961-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: eIhegNukVclMZDzaGzGl9cEScyM_duSV X-Proofpoint-ORIG-GUID: eIhegNukVclMZDzaGzGl9cEScyM_duSV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-13_03,2022-12-13_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 phishscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212130199 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, Kuogee Hsieh , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" By default, HBR2 (5.4G) is the max link link be supported. This patch uses the actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that. Changes in v2: -- add max link rate from dtsi Changes in v3: -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint Changes in v4: -- delete unnecessary pr_err Changes in v5: -- split parser function into different patch Changes in v9: -- revised commit test Changes in v13: -- repalced "properity" with "property" Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bfd0aef..edee550 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) struct edid *edid; dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; + dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; + + drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", + dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..1800d89 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; + /* Limit data lanes from data-lanes of endpoint property of dtsi */ if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); + /* Limit link rate from link-frequencies of endpoint property of dtsi */ + if (link_info->rate > dp_panel->max_dp_link_rate) + link_info->rate = dp_panel->max_dp_link_rate; drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index d861197a..f04d021 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct dp_panel { u32 vic; u32 max_dp_lanes; + u32 max_dp_link_rate; u32 max_bw_code; };