From patchwork Tue May 30 16:31:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 13260725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 956AAC7EE2E for ; Tue, 30 May 2023 16:32:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7178B10E3F9; Tue, 30 May 2023 16:32:26 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8112E10E3EA; Tue, 30 May 2023 16:32:22 +0000 (UTC) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34UFUjqk014323; Tue, 30 May 2023 16:32:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=sWvRueavxJ7CFVwUEv7MzgXSaCW+bmJGEmngToVWg4s=; b=mL3cJLCYZogiqDjtum5rydBcPAmWez3+Wr40bWFIxMqunU6GOfxwoVoudqb6WUaLRQzu 39cGKKSJg3ei5sYEY4AS7sa9RtFgzDyGA1JaFX+GGm9bUOWZVoQnjbzn7UnVgG8RJnAH hkj+qB1czPi96TCDeVI7JRa0POTR2R4Jd4Qc/Vnb0A/D1dzyzC9qW5lkriLbwymURP+5 rKBImNz1glimrwRA2MxF/GGXH6sBouMB/btol5MHyq40alBa4TRok3VEoOGjJIewke1w 58c5R/s76JHfy1GgqbGTcBZ9CdawcW+B19+QjLZJjXYOkWz/jxNE5i1NF1f8wkTjXbSH QQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qvv7nttqa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 May 2023 16:32:16 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34UGWG8S023282 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 May 2023 16:32:16 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 30 May 2023 09:32:15 -0700 From: Kuogee Hsieh To: , , , , , , , , , , Subject: [PATCH v1 3/3] drm/msm/dpu: remove msm_dsi_get_dsc_config() Date: Tue, 30 May 2023 09:31:58 -0700 Message-ID: <1685464318-25031-4-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1685464318-25031-1-git-send-email-quic_khsieh@quicinc.com> References: <1685464318-25031-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dyZeYl_Mtzd325OXZsUsCgU9PRF_cC1S X-Proofpoint-GUID: dyZeYl_Mtzd325OXZsUsCgU9PRF_cC1S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_12,2023-05-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305300131 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, Kuogee Hsieh , marijn.suijten@somainline.org, quic_jesszhan@quicinc.com, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since msm_dsi_bridge_get_dsc_config() was added to retrieve DSI DSC info through DRM bridge, msm_dsi_get_dsc_config() become redundant and should be removed. Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- drivers/gpu/drm/msm/dsi/dsi.c | 5 ----- drivers/gpu/drm/msm/msm_drv.h | 6 ------ 5 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 2927d20..1974d61 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2335,8 +2335,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, dpu_enc->idle_pc_supported = dpu_kms->catalog->caps->has_idle_pc; - dpu_enc->dsc = disp_info->dsc; - mutex_lock(&dpu_enc->enc_lock); for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 2c9ef8d..03a9ca0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,7 +28,6 @@ * @is_cmd_mode Boolean to indicate if the CMD mode is requested * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is * used instead of panel TE in cmd mode panels - * @dsc: DSC configuration data for DSC-enabled displays */ struct msm_display_info { int intf_type; @@ -36,7 +35,6 @@ struct msm_display_info { uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; bool is_te_using_watchdog_timer; - struct drm_dsc_config *dsc; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index c24f487..2390e5c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -554,8 +554,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, info.h_tile_instance[info.num_of_h_tiles++] = i; info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]); - if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); if (rc) { diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index fa7fcb5..154f19e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -12,11 +12,6 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) return !(host_flags & MIPI_DSI_MODE_VIDEO); } -struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) -{ - return msm_dsi_host_get_dsc_config(msm_dsi->host); -} - struct drm_dsc_config *msm_dsi_bridge_get_dsc_config(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5a7c1f4..8792e98 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -340,7 +340,6 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); -struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); struct drm_dsc_config *msm_dsi_bridge_get_dsc_config(struct drm_bridge *bridge); #else static inline void __init msm_dsi_register(void) @@ -371,11 +370,6 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) return false; } -static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) -{ - return NULL; -} - struct drm_dsc_config *msm_dsi_bridge_get_dsc_config(struct drm_bridge *bridge) { return NULL;