@@ -428,6 +428,15 @@ static void pch_irq_handler(struct drm_device *dev)
fdia = I915_READ(FDI_RXA_IIR);
fdib = I915_READ(FDI_RXB_IIR);
DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
+
+ if (fdia & FDI_RX_ERR_MASK) {
+ DRM_ERROR("FDI A RX error: 0x%08x\n", fdia);
+ I915_WRITE(FDI_RXA_IIR, FDI_RX_ERR_MASK);
+ }
+ if (fdib & FDI_RX_ERR_MASK) {
+ DRM_ERROR("FDI B RX error: 0x%08x\n", fdib);
+ I915_WRITE(FDI_RXB_IIR, FDI_RX_ERR_MASK);
+ }
}
if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
@@ -437,9 +446,9 @@ static void pch_irq_handler(struct drm_device *dev)
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
- DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
+ DRM_ERROR("PCH transcoder B underrun interrupt\n");
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
- DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
+ DRM_ERROR("PCH transcoder A underrun interrupt\n");
}
static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
@@ -3101,6 +3101,11 @@
#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
+#define FDI_RX_ERR_MASK (FDI_RX_FS_CODE_ERR | FDI_RX_FE_CODE_ERR | \
+ FDI_RX_SYMBOL_ERR_RATE_ABOVE | \
+ FDI_RX_PIXEL_FIFO_OVERFLOW | \
+ FDI_RX_CROSS_CLOCK_OVERFLOW | \
+ FDI_RX_SYMBOL_QUEUE_OVERFLOW)
#define FDI_RXA_IIR 0xf0014
#define FDI_RXA_IMR 0xf0018