From patchwork Wed May 29 22:15:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Glisse X-Patchwork-Id: 2632901 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id DD8F440077 for ; Wed, 29 May 2013 22:19:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C252E654D for ; Wed, 29 May 2013 15:19:04 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qc0-f178.google.com (mail-qc0-f178.google.com [209.85.216.178]) by gabe.freedesktop.org (Postfix) with ESMTP id C284EE5F70 for ; Wed, 29 May 2013 15:18:45 -0700 (PDT) Received: by mail-qc0-f178.google.com with SMTP id l11so5058192qcy.37 for ; Wed, 29 May 2013 15:18:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:subject:message-id:mime-version:content-type :content-disposition:user-agent; bh=YrpClABNrgUmRml+7Dq1OL5DVqBB1NS7TiZA8MRDxSk=; b=p0NWftALghZ5imit46Akch3Wi48xPmfKQULRuL+WYmYv7nd9EpevHz5T27IaMRcEHZ XgHnS8AB+RFTpnsqzO9vBfMBTaf7nB3vQnjRRXjEdPYkvdDSZX3BLUJ/kX0Ct5Vl+d1T Zmo3hpOOd/UcBaDXdH1QiPYMbxJZc2t/pNUa6c5etXiv/dXR+gtHr7LQeR6yOf7X0RDF 7uHGYXxFo0GBSrDmfz15DnwNaydBXXUgpZe5o9WJPq/hm1LJ3ulMMyx82jm1jREY7aZI VUW5NDj5hBJVGawWTjvVD+j9pap/soja5gVcFw80PcQ4DvjVTQ10Ur5+kadjaPjJexan 7iOg== X-Received: by 10.49.38.169 with SMTP id h9mr5223631qek.54.1369865925094; Wed, 29 May 2013 15:18:45 -0700 (PDT) Received: from gmail.com ([66.187.233.206]) by mx.google.com with ESMTPSA id y1sm33536703qad.5.2013.05.29.15.18.44 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 29 May 2013 15:18:44 -0700 (PDT) Date: Wed, 29 May 2013 18:15:15 -0400 From: Jerome Glisse To: dri-devel@lists.freedesktop.org Subject: radeon important ppc fix Message-ID: <20130529221514.GA4449@gmail.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Hi Dave, Can you please apply attached patch, it needs the following commit that is available in Linus git : d82fb31abc46620b7c22758c75707069f2763646 Cheers, Jerome From af30cf3e368733d69529c76a8db1df51ebdb42b5 Mon Sep 17 00:00:00 2001 From: Kleber Sacilotto de Souza Date: Fri, 3 May 2013 19:43:13 -0300 Subject: [PATCH] radeon: use max_bus_speed to activate gen2 speeds radeon currently uses a drm function to get the speed capabilities for the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard method of performing this detection and this patch changes it to use the max_bus_speed attribute. From: Lucas Kannebley Tavares Signed-off-by: Kleber Sacilotto de Souza --- drivers/gpu/drm/radeon/evergreen.c | 10 +++------- drivers/gpu/drm/radeon/r600.c | 9 ++------- drivers/gpu/drm/radeon/rv770.c | 9 ++------- 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 8f9e2d3..8546e3b 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev) void evergreen_pcie_gen2_enable(struct radeon_device *rdev) { - u32 link_width_cntl, speed_cntl, mask; - int ret; + u32 link_width_cntl, speed_cntl; if (radeon_pcie_gen2 == 0) return; @@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) if (ASIC_IS_X2(rdev)) return; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret != 0) - return; - - if (!(mask & DRM_PCIE_SPEED_50)) + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) return; speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 1a08008..b45e648 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) { u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; u16 link_cntl2; - u32 mask; - int ret; if (radeon_pcie_gen2 == 0) return; @@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) if (rdev->family <= CHIP_R600) return; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret != 0) - return; - - if (!(mask & DRM_PCIE_SPEED_50)) + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) return; speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 83f612a..a6af4aa 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -2113,8 +2113,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) { u32 link_width_cntl, lanes, speed_cntl, tmp; u16 link_cntl2; - u32 mask; - int ret; if (radeon_pcie_gen2 == 0) return; @@ -2129,11 +2127,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) if (ASIC_IS_X2(rdev)) return; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret != 0) - return; - - if (!(mask & DRM_PCIE_SPEED_50)) + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) return; DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");