From patchwork Thu Apr 24 20:15:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 4053671 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7456ABFF02 for ; Thu, 24 Apr 2014 20:15:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 949EF20306 for ; Thu, 24 Apr 2014 20:15:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7DDB7201BB for ; Thu, 24 Apr 2014 20:15:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD0CB6E0E7; Thu, 24 Apr 2014 13:15:40 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [87.106.93.118]) by gabe.freedesktop.org (Postfix) with ESMTP id C77656E0E7; Thu, 24 Apr 2014 13:15:39 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.73.22; Received: from nuc-i3427.alporthouse.com (unverified [78.156.73.22]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 24271503-1500048 for multiple; Thu, 24 Apr 2014 21:15:50 +0100 Received: by nuc-i3427.alporthouse.com (sSMTP sendmail emulation); Thu, 24 Apr 2014 21:15:21 +0100 Date: Thu, 24 Apr 2014 21:15:21 +0100 From: Chris Wilson To: Pavel Machek Subject: Re: [bisect result] Re: 3.15-rc2: i915 regression: only top 20% of screen works in X Message-ID: <20140424201521.GN31221@nuc-i3427.alporthouse.com> Mail-Followup-To: Chris Wilson , Pavel Machek , Daniel Vetter , intel-gfx , "Rafael J. Wysocki" , dri-devel , kernel list , Jiri Kosina References: <20140423202248.GA3621@amd.pavel.ucw.cz> <20140423220952.GA3627@amd.pavel.ucw.cz> <20140424055023.GA31221@nuc-i3427.alporthouse.com> <20140424194037.GB30333@amd.pavel.ucw.cz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140424194037.GB30333@amd.pavel.ucw.cz> User-Agent: Mutt/1.5.21 (2010-09-15) Cc: Daniel Vetter , intel-gfx , "Rafael J. Wysocki" , kernel list , dri-devel , Jiri Kosina X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Apr 24, 2014 at 09:40:38PM +0200, Pavel Machek wrote: > Hi! > > > And if you can indeed reliably reproduce this a bisect could be really useful. > > And we have a winner here :-) > > Ok, it was not as painfull as I feared. > > It does not revert cleanly, but doing it by hand was not that bad. Oh my. That is bizarre, can you check whether you have commit 9991ae787a0c87fe7c783b4b6f4754c3cdbb6213 Author: Chris Wilson Date: Wed Apr 2 16:36:07 2014 +0100 drm/i915: Move all ring resets before setting the HWS page in your latest kernel? That just makes > commit a51435a3137ad8ae75c288c39bd2d8b2696bae8f > Author: Naresh Kumar Kachhi > Date: Wed Mar 12 16:39:40 2014 +0530 > > drm/i915: disable rings before HW status page setup more consistent wrt g4x. To confirm, on drm-intel-nightly you used a patch like: Tested-by: Pavel Machek diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 36a62af..ce6186a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -494,6 +494,11 @@ static int init_ring_common(struct intel_ring_buffer *ring) I915_READ_TAIL(ring), I915_READ_START(ring)); + if (I915_NEED_GFX_HWS(dev)) + intel_ring_setup_status_page(ring); + else + ring_setup_phys_status_page(ring); + if (!stop_ring(ring)) { /* G45 ring initialization often fails to reset head to zero */ DRM_DEBUG_KMS("%s head not reset to zero " @@ -517,11 +522,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) } } - if (I915_NEED_GFX_HWS(dev)) - intel_ring_setup_status_page(ring); - else - ring_setup_phys_status_page(ring); - reset: /* Initialize the ring. This must happen _after_ we've cleared the ring * registers with the above sequence (the readback of the HEAD registers