From patchwork Thu Sep 1 11:23:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 9310321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A5CC60865 for ; Fri, 2 Sep 2016 02:00:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A757295BE for ; Fri, 2 Sep 2016 02:00:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6EF862957E; Fri, 2 Sep 2016 02:00:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 08E14295BE for ; Fri, 2 Sep 2016 02:00:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32A526EA2A; Fri, 2 Sep 2016 01:59:35 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by gabe.freedesktop.org (Postfix) with ESMTPS id B28F26E909 for ; Thu, 1 Sep 2016 11:30:06 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u81BO6nU026419; Thu, 1 Sep 2016 06:24:06 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u81BO5aM024592; Thu, 1 Sep 2016 06:24:05 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Thu, 1 Sep 2016 06:24:05 -0500 Received: from dlep33.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u81BNMx0024982; Thu, 1 Sep 2016 06:24:03 -0500 From: Peter Ujfalusi To: , , Subject: [PATCH 17/26] drm/omap: omap_display_timings: Use display_flags for double_pixel mode Date: Thu, 1 Sep 2016 14:23:11 +0300 Message-ID: <20160901112320.15246-18-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160901112320.15246-1-peter.ujfalusi@ti.com> References: <20160901112320.15246-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 02 Sep 2016 01:59:29 +0000 Cc: daniel.vetter@ffwll.ch, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP In preparation to move the stack to use the generic videmode struct for display timing information. Signed-off-by: Peter Ujfalusi --- drivers/gpu/drm/omapdrm/dss/dispc.c | 6 +++--- drivers/gpu/drm/omapdrm/dss/hdmi4.c | 2 +- drivers/gpu/drm/omapdrm/dss/hdmi5.c | 2 +- drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++-- drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 3 +-- drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 -- drivers/gpu/drm/omapdrm/omap_connector.c | 5 +++-- 7 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index ae1e25b33391..39a9c34694f5 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -3270,8 +3270,9 @@ void dispc_mgr_set_timings(enum omap_channel channel, t.vactive /= 2; if (dispc.feat->supports_double_pixel) - REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0, - 19, 17); + REG_FLD_MOD(DISPC_CONTROL, + !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), + 19, 17); } dispc_mgr_set_size(channel, t.hactive, t.vactive); @@ -4206,7 +4207,6 @@ static const struct dispc_errata_i734_data { .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, - .double_pixel = false, .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH, diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c index 2a5a71a25423..891518502d3d 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c @@ -175,7 +175,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) p->vactive); pc = p->pixelclock; - if (p->double_pixel) + if (p->flags & DISPLAY_FLAGS_DOUBLECLK) pc *= 2; /* DSS_HDMI_TCLK is bitclk / 10 */ diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c index 45f445523a4f..8206ef69caf1 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c @@ -187,7 +187,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) p->vactive); pc = p->pixelclock; - if (p->double_pixel) + if (p->flags & DISPLAY_FLAGS_DOUBLECLK) pc *= 2; /* DSS_HDMI_TCLK is bitclk / 10 */ diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c index f64f389939d1..e86972b98a91 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c @@ -315,7 +315,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, video_cfg->v_fc_config.timings.vback_porch /= 2; } - if (cfg->timings.double_pixel) { + if (cfg->timings.flags & DISPLAY_FLAGS_DOUBLECLK) { video_cfg->v_fc_config.timings.hactive *= 2; video_cfg->hblank *= 2; video_cfg->v_fc_config.timings.hfront_porch *= 2; @@ -382,7 +382,7 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, cfg->v_fc_config.hdmi_dvi_mode, 3, 3); - if (ovt->double_pixel) + if (ovt->flags & DISPLAY_FLAGS_DOUBLECLK) REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); else REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index b86e5a357456..20effa9260ec 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c @@ -208,7 +208,6 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, timings->vfront_porch = param->timings.vfront_porch; timings->vsync_len = param->timings.vsync_len; - timings->double_pixel = param->timings.double_pixel; timings->flags = param->timings.flags; if (param->timings.flags & DISPLAY_FLAGS_INTERLACED) { @@ -218,7 +217,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, timings->vsync_len /= 2; } - if (param->timings.double_pixel) { + if (param->timings.flags & DISPLAY_FLAGS_DOUBLECLK) { video_fmt->x_res *= 2; timings->hfront_porch *= 2; timings->hsync_len *= 2; diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 4aa8ebfa69fc..b14d2a72b966 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -324,8 +324,6 @@ struct omap_video_timings { /* Pixel clock edges to drive HSYNC and VSYNC signals */ enum omap_dss_signal_edge sync_pclk_edge; - bool double_pixel; - enum display_flags flags; /* display flags */ }; diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c index 8817e38761ae..f3e9bcf1f784 100644 --- a/drivers/gpu/drm/omapdrm/omap_connector.c +++ b/drivers/gpu/drm/omapdrm/omap_connector.c @@ -62,7 +62,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode, if (timings->flags & DISPLAY_FLAGS_INTERLACED) mode->flags |= DRM_MODE_FLAG_INTERLACE; - if (timings->double_pixel) + if (timings->flags & DISPLAY_FLAGS_DOUBLECLK) mode->flags |= DRM_MODE_FLAG_DBLCLK; if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH) @@ -94,7 +94,8 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings, if (mode->flags & DRM_MODE_FLAG_INTERLACE) timings->flags |= DISPLAY_FLAGS_INTERLACED; - timings->double_pixel = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + timings->flags |= DISPLAY_FLAGS_DOUBLECLK; if (mode->flags & DRM_MODE_FLAG_PHSYNC) timings->flags |= DISPLAY_FLAGS_HSYNC_HIGH;