From patchwork Thu Sep 22 11:06:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 9345593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 939ED60B16 for ; Thu, 22 Sep 2016 15:30:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8581827D0E for ; Thu, 22 Sep 2016 15:30:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7A56B2AA93; Thu, 22 Sep 2016 15:30:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2587927D0E for ; Thu, 22 Sep 2016 15:30:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CEDC6E8D7; Thu, 22 Sep 2016 15:30:08 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from bear.ext.ti.com (bear.ext.ti.com [198.47.19.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 81B706E01B for ; Thu, 22 Sep 2016 13:31:36 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8MB7ZnT004672; Thu, 22 Sep 2016 06:07:35 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8MB7Z1e023594; Thu, 22 Sep 2016 06:07:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Thu, 22 Sep 2016 06:07:34 -0500 Received: from dflp33.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8MB79j4024995; Thu, 22 Sep 2016 06:07:33 -0500 From: Peter Ujfalusi To: , , Subject: [PATCH v2 11/23] drm/omap: dispc: Simplify _dispc_mgr_set_lcd_timings() parameters Date: Thu, 22 Sep 2016 14:06:56 +0300 Message-ID: <20160922110708.31242-12-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20160922110708.31242-1-peter.ujfalusi@ti.com> References: <20160922110708.31242-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 22 Sep 2016 15:29:45 +0000 Cc: daniel.vetter@ffwll.ch, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of passing the omap_video_timings structure's members individually, use the pointer to the struct. Signed-off-by: Peter Ujfalusi --- drivers/gpu/drm/omapdrm/dss/dispc.c | 38 ++++++++++++++----------------------- 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 858d87dd7fe8..e29f33fd19cd 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -3141,29 +3141,23 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, return true; } -static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, - int hfp, int hbp, int vsw, int vfp, int vbp, - enum omap_dss_signal_level vsync_level, - enum omap_dss_signal_level hsync_level, - enum omap_dss_signal_edge data_pclk_edge, - enum omap_dss_signal_level de_level, - enum omap_dss_signal_edge sync_pclk_edge) - +static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, + const struct omap_video_timings *ovt) { u32 timing_h, timing_v, l; bool onoff, rf, ipc, vs, hs, de; - timing_h = FLD_VAL(hsync_len-1, dispc.feat->sw_start, 0) | - FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | - FLD_VAL(hbp-1, dispc.feat->bp_start, 20); - timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | - FLD_VAL(vfp, dispc.feat->fp_start, 8) | - FLD_VAL(vbp, dispc.feat->bp_start, 20); + timing_h = FLD_VAL(ovt->hsync_len - 1, dispc.feat->sw_start, 0) | + FLD_VAL(ovt->hfront_porch - 1, dispc.feat->fp_start, 8) | + FLD_VAL(ovt->hback_porch - 1, dispc.feat->bp_start, 20); + timing_v = FLD_VAL(ovt->vsync_len - 1, dispc.feat->sw_start, 0) | + FLD_VAL(ovt->vfront_porch, dispc.feat->fp_start, 8) | + FLD_VAL(ovt->vback_porch, dispc.feat->bp_start, 20); dispc_write_reg(DISPC_TIMING_H(channel), timing_h); dispc_write_reg(DISPC_TIMING_V(channel), timing_v); - switch (vsync_level) { + switch (ovt->vsync_level) { case OMAPDSS_SIG_ACTIVE_LOW: vs = true; break; @@ -3174,7 +3168,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, BUG(); } - switch (hsync_level) { + switch (ovt->hsync_level) { case OMAPDSS_SIG_ACTIVE_LOW: hs = true; break; @@ -3185,7 +3179,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, BUG(); } - switch (de_level) { + switch (ovt->de_level) { case OMAPDSS_SIG_ACTIVE_LOW: de = true; break; @@ -3196,7 +3190,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, BUG(); } - switch (data_pclk_edge) { + switch (ovt->data_pclk_edge) { case OMAPDSS_DRIVE_SIG_RISING_EDGE: ipc = false; break; @@ -3210,7 +3204,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, /* always use the 'rf' setting */ onoff = true; - switch (sync_pclk_edge) { + switch (ovt->sync_pclk_edge) { case OMAPDSS_DRIVE_SIG_FALLING_EDGE: rf = false; break; @@ -3270,11 +3264,7 @@ void dispc_mgr_set_timings(enum omap_channel channel, } if (dss_mgr_is_lcd(channel)) { - _dispc_mgr_set_lcd_timings(channel, - t.hsync_len, t.hfront_porch, t.hback_porch, - t.vsync_len, t.vfront_porch, t.vback_porch, - t.vsync_level, t.hsync_level, t.data_pclk_edge, - t.de_level, t.sync_pclk_edge); + _dispc_mgr_set_lcd_timings(channel, &t); xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;