diff mbox

[2/8] drm/tegra: Allocate BOs from lower 4G when without IOMMU

Message ID 20161110182345.31777-3-mperttunen@nvidia.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mikko Perttunen Nov. 10, 2016, 6:23 p.m. UTC
On 64-bit Tegras, buffer object memory allocation may
return memory above 4G that units behind Host1x cannot
access. Add the GFP_DMA flag to these allocation when
IOMMU is not enabled to ensure units can always access
BO memory.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/drm/tegra/gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Thierry Reding Dec. 5, 2016, 6:39 p.m. UTC | #1
On Thu, Nov 10, 2016 at 08:23:39PM +0200, Mikko Perttunen wrote:
> On 64-bit Tegras, buffer object memory allocation may
> return memory above 4G that units behind Host1x cannot
> access. Add the GFP_DMA flag to these allocation when
> IOMMU is not enabled to ensure units can always access
> BO memory.

I don't think that's entirely true. The display controller can address
more than 32 bits. It's perhaps slightly different from other units that
are behind host1x, but maybe we need a special case here to allow frame-
buffers to reside in higher memory?

Thierry
Mikko Perttunen Dec. 7, 2016, 9:32 a.m. UTC | #2
On 05.12.2016 20:39, Thierry Reding wrote:
> On Thu, Nov 10, 2016 at 08:23:39PM +0200, Mikko Perttunen wrote:
>> On 64-bit Tegras, buffer object memory allocation may
>> return memory above 4G that units behind Host1x cannot
>> access. Add the GFP_DMA flag to these allocation when
>> IOMMU is not enabled to ensure units can always access
>> BO memory.
>
> I don't think that's entirely true. The display controller can address
> more than 32 bits. It's perhaps slightly different from other units that
> are behind host1x, but maybe we need a special case here to allow frame-
> buffers to reside in higher memory?

I checked and looks like all (or at least most) units can actually 
address 34 bits /almost always/. The thing that tripped me up was that 
apparently the firmware for VIC still needs be in the lower 32 bits. So 
we should be able to drop this patch.

>
> Thierry
>

Thanks,
Mikko.
diff mbox

Patch

diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 19bf9cd..e36e6c5 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -233,7 +233,7 @@  static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo)
 		size_t size = bo->gem.size;
 
 		bo->vaddr = dma_alloc_wc(drm->dev, size, &bo->paddr,
-					 GFP_KERNEL | __GFP_NOWARN);
+					 GFP_KERNEL | GFP_DMA | __GFP_NOWARN);
 		if (!bo->vaddr) {
 			dev_err(drm->dev,
 				"failed to allocate buffer of size %zu\n",