| Message ID | 20170126153217.26916-1-p.zabel@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jan 26, 2017 at 04:32:17PM +0100, Philipp Zabel wrote: > Vivante GC hardware uses simple 4x4 tiled and nested 64x64 supertiled > formats as well as so-called split-tiled variants for dual-pipe > hardware, where even and odd tiles start at different base addresses. > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > --- > include/uapi/drm/drm_fourcc.h | 41 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index a5890bf44c0af..ec0498cf61756 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -159,6 +159,7 @@ extern "C" { > #define DRM_FORMAT_MOD_VENDOR_NV 0x03 > #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 > #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 > +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 > /* add more to the end as needed */ > > #define fourcc_mod_code(vendor, val) \ > @@ -233,6 +234,46 @@ extern "C" { > */ > #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) > > +/* Vivante framebuffer modifiers */ > + > +/* > + * Vivante 4x4 tiling layout > + * > + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major > + * layout. > + */ > +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) > + > +/* > + * Vivante 64x64 super-tiling layout > + * > + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile > + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- > + * major layout. > + * > + * For more information: see > + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling > + */ > +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) > + > +/* > + * Vivante 4x4 tiling layout for dual-pipe > + * > + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a > + * different base address. Offsets from the base addresses are therefore halved > + * compared to the non-split tiled layout. > + */ > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) > + > +/* > + * Vivante 64x64 super-tiling layout for dual-pipe > + * > + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile > + * starts at a different base address. Offsets from the base addresses are > + * therefore halved compared to the non-split super-tiled layout. > + */ > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) Does this mean the dual-pipe stuff has 2 planes? Do you need Ville's driver-private format stuff for this? Also, someone else with clue needs to review this before I can pull it in :-) -Daniel > + > #if defined(__cplusplus) > } > #endif > -- > 2.11.0 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com> I do wonder whether we'll need the split formats in practice - e.g. the GC3000 on the i.MX6qp, for which I suppose this is being done because of tiled buffers support in the PRE, has the "single buffer" feature which allows rendering to a single buffer with multiple pixel pipes. This is what the Vivante driver uses. But it can't hurt reserving formats for them. Wladimir > > Vivante GC hardware uses simple 4x4 tiled and nested 64x64 supertiled > > formats as well as so-called split-tiled variants for dual-pipe > > hardware, where even and odd tiles start at different base addresses. > > > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > --- > > include/uapi/drm/drm_fourcc.h | 41 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index a5890bf44c0af..ec0498cf61756 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -159,6 +159,7 @@ extern "C" { > > #define DRM_FORMAT_MOD_VENDOR_NV 0x03 > > #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 > > #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 > > +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 > > /* add more to the end as needed */ > > > > #define fourcc_mod_code(vendor, val) \ > > @@ -233,6 +234,46 @@ extern "C" { > > */ > > #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) > > > > +/* Vivante framebuffer modifiers */ > > + > > +/* > > + * Vivante 4x4 tiling layout > > + * > > + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major > > + * layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) > > + > > +/* > > + * Vivante 64x64 super-tiling layout > > + * > > + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile > > + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- > > + * major layout. > > + * > > + * For more information: see > > + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) > > + > > +/* > > + * Vivante 4x4 tiling layout for dual-pipe > > + * > > + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a > > + * different base address. Offsets from the base addresses are therefore halved > > + * compared to the non-split tiled layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) > > + > > +/* > > + * Vivante 64x64 super-tiling layout for dual-pipe > > + * > > + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile > > + * starts at a different base address. Offsets from the base addresses are > > + * therefore halved compared to the non-split super-tiled layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) > > Does this mean the dual-pipe stuff has 2 planes? Do you need Ville's > driver-private format stuff for this? > > Also, someone else with clue needs to review this before I can pull it in > :-) > -Daniel > > > + > > #if defined(__cplusplus) > > } > > #endif > > -- > > 2.11.0 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch
On Thu, Jan 26, 2017 at 07:29:13PM +0100, Wladimir J. van der Laan wrote: > > Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com> > > I do wonder whether we'll need the split formats in practice - > e.g. the GC3000 on the i.MX6qp, for which I suppose this is being done because > of tiled buffers support in the PRE, has the "single buffer" feature > which allows rendering to a single buffer with multiple pixel pipes. > This is what the Vivante driver uses. > > But it can't hurt reserving formats for them. Yeah, no harm in reserving&documenting them. Patch applied to drm-misc, I'll probably only do a pull request for it early next week due to -rc6 backmerge reasons. -Daniel > > Wladimir > > > > Vivante GC hardware uses simple 4x4 tiled and nested 64x64 supertiled > > > formats as well as so-called split-tiled variants for dual-pipe > > > hardware, where even and odd tiles start at different base addresses. > > > > > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > > --- > > > include/uapi/drm/drm_fourcc.h | 41 +++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 41 insertions(+) > > > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > > index a5890bf44c0af..ec0498cf61756 100644 > > > --- a/include/uapi/drm/drm_fourcc.h > > > +++ b/include/uapi/drm/drm_fourcc.h > > > @@ -159,6 +159,7 @@ extern "C" { > > > #define DRM_FORMAT_MOD_VENDOR_NV 0x03 > > > #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 > > > #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 > > > +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 > > > /* add more to the end as needed */ > > > > > > #define fourcc_mod_code(vendor, val) \ > > > @@ -233,6 +234,46 @@ extern "C" { > > > */ > > > #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) > > > > > > +/* Vivante framebuffer modifiers */ > > > + > > > +/* > > > + * Vivante 4x4 tiling layout > > > + * > > > + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major > > > + * layout. > > > + */ > > > +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) > > > + > > > +/* > > > + * Vivante 64x64 super-tiling layout > > > + * > > > + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile > > > + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- > > > + * major layout. > > > + * > > > + * For more information: see > > > + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling > > > + */ > > > +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) > > > + > > > +/* > > > + * Vivante 4x4 tiling layout for dual-pipe > > > + * > > > + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a > > > + * different base address. Offsets from the base addresses are therefore halved > > > + * compared to the non-split tiled layout. > > > + */ > > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) > > > + > > > +/* > > > + * Vivante 64x64 super-tiling layout for dual-pipe > > > + * > > > + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile > > > + * starts at a different base address. Offsets from the base addresses are > > > + * therefore halved compared to the non-split super-tiled layout. > > > + */ > > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) > > > > Does this mean the dual-pipe stuff has 2 planes? Do you need Ville's > > driver-private format stuff for this? > > > > Also, someone else with clue needs to review this before I can pull it in > > :-) > > -Daniel > > > > > + > > > #if defined(__cplusplus) > > > } > > > #endif > > > -- > > > 2.11.0 > > > > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch
Am Donnerstag, den 26.01.2017, 18:24 +0100 schrieb Daniel Vetter: > On Thu, Jan 26, 2017 at 04:32:17PM +0100, Philipp Zabel wrote: > > Vivante GC hardware uses simple 4x4 tiled and nested 64x64 supertiled > > formats as well as so-called split-tiled variants for dual-pipe > > hardware, where even and odd tiles start at different base addresses. > > > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > --- > > include/uapi/drm/drm_fourcc.h | 41 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index a5890bf44c0af..ec0498cf61756 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -159,6 +159,7 @@ extern "C" { > > #define DRM_FORMAT_MOD_VENDOR_NV 0x03 > > #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 > > #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 > > +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 > > /* add more to the end as needed */ > > > > #define fourcc_mod_code(vendor, val) \ > > @@ -233,6 +234,46 @@ extern "C" { > > */ > > #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) > > > > +/* Vivante framebuffer modifiers */ > > + > > +/* > > + * Vivante 4x4 tiling layout > > + * > > + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major > > + * layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) > > + > > +/* > > + * Vivante 64x64 super-tiling layout > > + * > > + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile > > + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- > > + * major layout. > > + * > > + * For more information: see > > + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) > > + > > +/* > > + * Vivante 4x4 tiling layout for dual-pipe > > + * > > + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a > > + * different base address. Offsets from the base addresses are therefore halved > > + * compared to the non-split tiled layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) > > + > > +/* > > + * Vivante 64x64 super-tiling layout for dual-pipe > > + * > > + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile > > + * starts at a different base address. Offsets from the base addresses are > > + * therefore halved compared to the non-split super-tiled layout. > > + */ > > +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) > > Does this mean the dual-pipe stuff has 2 planes? Do you need Ville's > driver-private format stuff for this? Nope, it's a single plane, but the pipes using different offsets within the plane. As the pipe address registers are freely configurable we could push the render output into 2 planes, but why make our life hard for no reason? :) Regards, Lucas
On Thu, 2017-01-26 at 19:29 +0100, Wladimir J. van der Laan wrote: > Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com> Thank you. > I do wonder whether we'll need the split formats in practice - > e.g. the GC3000 on the i.MX6qp, for which I suppose this is being done because > of tiled buffers support in the PRE, has the "single buffer" feature > which allows rendering to a single buffer with multiple pixel pipes. > This is what the Vivante driver uses. > > But it can't hurt reserving formats for them. I added them in case it later turns out that avoiding the resolve copy is advantageous on GC2000 in combination with USB DisplayLink style outputs, where the CPU could directly process the split-tiled buffers. regards Philipp
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index a5890bf44c0af..ec0498cf61756 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -159,6 +159,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_NV 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 /* add more to the end as needed */ #define fourcc_mod_code(vendor, val) \ @@ -233,6 +234,46 @@ extern "C" { */ #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) +/* Vivante framebuffer modifiers */ + +/* + * Vivante 4x4 tiling layout + * + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) + +/* + * Vivante 64x64 super-tiling layout + * + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- + * major layout. + * + * For more information: see + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling + */ +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) + +/* + * Vivante 4x4 tiling layout for dual-pipe + * + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a + * different base address. Offsets from the base addresses are therefore halved + * compared to the non-split tiled layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) + +/* + * Vivante 64x64 super-tiling layout for dual-pipe + * + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile + * starts at a different base address. Offsets from the base addresses are + * therefore halved compared to the non-split super-tiled layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) + #if defined(__cplusplus) } #endif
Vivante GC hardware uses simple 4x4 tiled and nested 64x64 supertiled formats as well as so-called split-tiled variants for dual-pipe hardware, where even and odd tiles start at different base addresses. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- include/uapi/drm/drm_fourcc.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)