From patchwork Wed Feb 22 15:18:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9587595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A5C29601AE for ; Thu, 23 Feb 2017 01:08:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9463128725 for ; Thu, 23 Feb 2017 01:08:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8775628727; Thu, 23 Feb 2017 01:08:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1487A28725 for ; Thu, 23 Feb 2017 01:08:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D7A16E926; Thu, 23 Feb 2017 01:07:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from forward9m.cmail.yandex.net (forward9m.cmail.yandex.net [5.255.216.202]) by gabe.freedesktop.org (Postfix) with ESMTPS id 254C16E843 for ; Wed, 22 Feb 2017 15:31:42 +0000 (UTC) Received: from smtp2o.mail.yandex.net (smtp2o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::26]) by forward9m.cmail.yandex.net (Yandex) with ESMTP id 49BAF21537; Wed, 22 Feb 2017 18:22:41 +0300 (MSK) Received: from smtp2o.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp2o.mail.yandex.net (Yandex) with ESMTP id A582350808F0; Wed, 22 Feb 2017 18:22:31 +0300 (MSK) Received: by smtp2o.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id ZbnmgsRLHQ-LNauodCJ; Wed, 22 Feb 2017 18:22:29 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1487776950; bh=YjFfwTpsK9DQVysdb+2/EWv+kclRt9qmnfm9wH7iVW0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=OQt0oESYuMlOFq1mHE/etGaoAdpkkuFROd/SfLnzW3qc7YK8mh11VSfqtRB6gQxbf XsTvDBlcKNtRc9NRP0oKjrkFMfaCnnpP2btiG4aZujP1Rq22ZVGyX7UbjCiGrBJNNv CHvKcqVm4GwagE0BeDdIfdH9h3+V6nesZ6Szdsak= Authentication-Results: smtp2o.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1130000036118848 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , David Airlie Subject: [PATCH 3/8] dt-bindings: add bindings for DE2 on V3s SoC Date: Wed, 22 Feb 2017 23:18:49 +0800 Message-Id: <20170222151854.3280-4-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170222151854.3280-1-icenowy@aosc.xyz> References: <20170222151854.3280-1-icenowy@aosc.xyz> X-Mailman-Approved-At: Thu, 23 Feb 2017 01:07:27 +0000 Cc: Jean-Francois Moine , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Icenowy Zheng , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Allwinner V3s SoC have a display engine which have a different pipeline with older SoCs. Add document for it (new compatibles and the new "mixer" part). The paragraph of TCON is also refactored, for furtherly add TCONs in A83T/H3/A64/H5 that have only a channel 1 (used for HDMI or TV Encoder). Signed-off-by: Icenowy Zheng --- .../bindings/display/sunxi/sun4i-drm.txt | 37 +++++++++++++++++++--- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index b82c00449468..2c293247c41d 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -31,11 +31,11 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon + * allwinner,sun8i-v3s-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. Three are needed: + - clocks: phandles to the clocks feeding the TCON - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0 - resets: phandles to the reset controllers driving the encoder - "lcd": the reset line for the TCON channel 0 @@ -52,7 +52,12 @@ Required properties: second the block connected to the TCON channel 1 (usually the TV encoder) -On SoCs other than the A33, there is one more clock required: +On TCONs that have a channel 0 (currently all TCONs supported), there +is one more clock required: + - 'tcon-ch0': The clock driving the TCON channel 0 + +On TCONs that have a channel 1 (currently all TCONs except the ones in +A33 and V3s), there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC @@ -137,6 +142,26 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoints, the second one the outputs +Display Engine 2.0 Mixer +------------------------ + +The DE2 mixer have many functionalities, currently only layer blending is +supported. + +Required properties: + - compatible: value must be one of: + * allwinner,sun8i-v3s-de2-mixer + - reg: base address and size of the memory-mapped region. + - clocks: phandles to the clocks feeding the frontend and backend + * bus: the backend interface clock + * ram: the backend DRAM clock + - clock-names: the clock names mentioned above + - resets: phandles to the reset controllers driving the backend + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoints, the second one the output + Display Engine Pipeline ----------------------- @@ -151,9 +176,13 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine + * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine - frontends available. + pipeline entry point. For SoCs with original DE (currently + all SoCs supported by display engine except V3s), this + phandle should be a display frontend or backend; for SoCs + with DE2, this phandle should be a mixer. Example: