diff mbox

[libdrm,1/3] headers: sync amdgpu_drm.h from airlied/drm-next

Message ID 20170403082720.13166-1-nhaehnle@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Nicolai Hähnle April 3, 2017, 8:27 a.m. UTC
From: Nicolai Hähnle <nicolai.haehnle@amd.com>

Changes include: PRT and preemption flags, sensor info, and some more
changes for Vega10.

Generated using make headers_install from airlied/drm-next commit
320d8c3d38739fa8e31a076b86cbdafcf8897d5e.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---
 include/drm/amdgpu_drm.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

Comments

Samuel Pitoiset April 3, 2017, 9:36 a.m. UTC | #1
On 04/03/2017 10:27 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle <nicolai.haehnle@amd.com>
>
> Changes include: PRT and preemption flags, sensor info, and some more
> changes for Vega10.

Cool, thanks. I will be able to re-send the sensor info series for mesa. :)

>
> Generated using make headers_install from airlied/drm-next commit
> 320d8c3d38739fa8e31a076b86cbdafcf8897d5e.
>
> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
> ---
>  include/drm/amdgpu_drm.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index fa56499..516a9f2 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -225,20 +225,21 @@ struct drm_amdgpu_gem_userptr {
>  #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
>  #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
>  #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
>
>  /* GFX9 and later: */
>  #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
>  #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
>
> +/* Set/Get helpers for tiling flags. */
>  #define AMDGPU_TILING_SET(field, value) \
>  	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
>  #define AMDGPU_TILING_GET(value, field) \
>  	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
>
>  #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
>  #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
>
>  /** The same structure is shared for input/output */
>  struct drm_amdgpu_gem_metadata {
> @@ -348,31 +349,47 @@ struct drm_amdgpu_gem_op {
>  	/** GEM object handle */
>  	__u32	handle;
>  	/** AMDGPU_GEM_OP_* */
>  	__u32	op;
>  	/** Input or return value */
>  	__u64	value;
>  };
>
>  #define AMDGPU_VA_OP_MAP			1
>  #define AMDGPU_VA_OP_UNMAP			2
> +#define AMDGPU_VA_OP_CLEAR			3
> +#define AMDGPU_VA_OP_REPLACE			4
>
>  /* Delay the page table update till the next CS */
>  #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
>
>  /* Mapping flags */
>  /* readable mapping */
>  #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
>  /* writable mapping */
>  #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
>  /* executable mapping, new for VI */
>  #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
> +/* partially resident texture */
> +#define AMDGPU_VM_PAGE_PRT		(1 << 4)
> +/* MTYPE flags use bit 5 to 8 */
> +#define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
> +/* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
> +#define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
> +/* Use NC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_NC		(1 << 5)
> +/* Use WC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_WC		(2 << 5)
> +/* Use CC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_CC		(3 << 5)
> +/* Use UC MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_UC		(4 << 5)
>
>  struct drm_amdgpu_gem_va {
>  	/** GEM object handle */
>  	__u32 handle;
>  	__u32 _pad;
>  	/** AMDGPU_VA_OP_* */
>  	__u32 operation;
>  	/** AMDGPU_VM_PAGE_* */
>  	__u32 flags;
>  	/** va address to assign . Must be correctly aligned.*/
> @@ -421,23 +438,26 @@ struct drm_amdgpu_cs_out {
>  union drm_amdgpu_cs {
>  	struct drm_amdgpu_cs_in in;
>  	struct drm_amdgpu_cs_out out;
>  };
>
>  /* Specify flags to be used for IB */
>
>  /* This IB should be submitted to CE */
>  #define AMDGPU_IB_FLAG_CE	(1<<0)
>
> -/* CE Preamble */
> +/* Preamble flag, which means the IB could be dropped if no context switch */
>  #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
>
> +/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
> +#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
> +
>  struct drm_amdgpu_cs_chunk_ib {
>  	__u32 _pad;
>  	/** AMDGPU_IB_FLAG_* */
>  	__u32 flags;
>  	/** Virtual address to begin IB execution */
>  	__u64 va_start;
>  	/** Size of submission */
>  	__u32 ib_bytes;
>  	/** HW IP to submit to */
>  	__u32 ip_type;
> @@ -499,20 +519,24 @@ struct drm_amdgpu_cs_chunk_data {
>  	/* Subquery id: Query GFX CE firmware version */
>  	#define AMDGPU_INFO_FW_GFX_CE		0x06
>  	/* Subquery id: Query GFX RLC firmware version */
>  	#define AMDGPU_INFO_FW_GFX_RLC		0x07
>  	/* Subquery id: Query GFX MEC firmware version */
>  	#define AMDGPU_INFO_FW_GFX_MEC		0x08
>  	/* Subquery id: Query SMC firmware version */
>  	#define AMDGPU_INFO_FW_SMC		0x0a
>  	/* Subquery id: Query SDMA firmware version */
>  	#define AMDGPU_INFO_FW_SDMA		0x0b
> +	/* Subquery id: Query PSP SOS firmware version */
> +	#define AMDGPU_INFO_FW_SOS		0x0c
> +	/* Subquery id: Query PSP ASD firmware version */
> +	#define AMDGPU_INFO_FW_ASD		0x0d
>  /* number of bytes moved for TTM migration */
>  #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
>  /* the used VRAM size */
>  #define AMDGPU_INFO_VRAM_USAGE			0x10
>  /* the used GTT size */
>  #define AMDGPU_INFO_GTT_USAGE			0x11
>  /* Information about GDS, etc. resource configuration */
>  #define AMDGPU_INFO_GDS_CONFIG			0x13
>  /* Query information about VRAM and GTT domains */
>  #define AMDGPU_INFO_VRAM_GTT			0x14
> @@ -529,20 +553,36 @@ struct drm_amdgpu_cs_chunk_data {
>  /* Query vce clock table */
>  #define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
>  /* Query vbios related information */
>  #define AMDGPU_INFO_VBIOS			0x1B
>  	/* Subquery id: Query vbios size */
>  	#define AMDGPU_INFO_VBIOS_SIZE		0x1
>  	/* Subquery id: Query vbios image */
>  	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
>  /* Query UVD handles */
>  #define AMDGPU_INFO_NUM_HANDLES			0x1C
> +/* Query sensor related information */
> +#define AMDGPU_INFO_SENSOR			0x1D
> +	/* Subquery id: Query GPU shader clock */
> +	#define AMDGPU_INFO_SENSOR_GFX_SCLK		0x1
> +	/* Subquery id: Query GPU memory clock */
> +	#define AMDGPU_INFO_SENSOR_GFX_MCLK		0x2
> +	/* Subquery id: Query GPU temperature */
> +	#define AMDGPU_INFO_SENSOR_GPU_TEMP		0x3
> +	/* Subquery id: Query GPU load */
> +	#define AMDGPU_INFO_SENSOR_GPU_LOAD		0x4
> +	/* Subquery id: Query average GPU power	*/
> +	#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER	0x5
> +	/* Subquery id: Query northbridge voltage */
> +	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
> +	/* Subquery id: Query graphics voltage */
> +	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
>
>  #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
>  #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
>  #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
>  #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
>
>  struct drm_amdgpu_query_fw {
>  	/** AMDGPU_INFO_FW_* */
>  	__u32 fw_type;
>  	/**
> @@ -592,20 +632,24 @@ struct drm_amdgpu_info {
>  			/** For future use, no flags defined so far */
>  			__u32 flags;
>  		} read_mmr_reg;
>
>  		struct drm_amdgpu_query_fw query_fw;
>
>  		struct {
>  			__u32 type;
>  			__u32 offset;
>  		} vbios_info;
> +
> +		struct {
> +			__u32 type;
> +		} sensor_info;
>  	};
>  };
>
>  struct drm_amdgpu_info_gds {
>  	/** GDS GFX partition size */
>  	__u32 gds_gfx_partition_size;
>  	/** GDS compute partition size */
>  	__u32 compute_partition_size;
>  	/** total GDS memory size */
>  	__u32 gds_total_size;
> @@ -703,20 +747,30 @@ struct drm_amdgpu_info_device {
>  	__u32 pte_fragment_size;
>  	__u32 gart_page_size;
>  	/** constant engine ram size*/
>  	__u32 ce_ram_size;
>  	/** video memory type info*/
>  	__u32 vram_type;
>  	/** video memory bit width*/
>  	__u32 vram_bit_width;
>  	/* vce harvesting instance */
>  	__u32 vce_harvest_config;
> +	/* gfx double offchip LDS buffers */
> +	__u32 gc_double_offchip_lds_buf;
> +	/* NGG Primitive Buffer */
> +	__u64 prim_buf_gpu_addr;
> +	/* NGG Position Buffer */
> +	__u64 pos_buf_gpu_addr;
> +	/* NGG Control Sideband */
> +	__u64 cntl_sb_buf_gpu_addr;
> +	/* NGG Parameter Cache */
> +	__u64 param_buf_gpu_addr;
>  };
>
>  struct drm_amdgpu_info_hw_ip {
>  	/** Version of h/w IP */
>  	__u32  hw_ip_version_major;
>  	__u32  hw_ip_version_minor;
>  	/** Capabilities */
>  	__u64  capabilities_flags;
>  	/** command buffer address start alignment*/
>  	__u32  ib_start_alignment;
>
diff mbox

Patch

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index fa56499..516a9f2 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -225,20 +225,21 @@  struct drm_amdgpu_gem_userptr {
 #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
 #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
 
 /* GFX9 and later: */
 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
 #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
 
+/* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \
 	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
 	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 
 /** The same structure is shared for input/output */
 struct drm_amdgpu_gem_metadata {
@@ -348,31 +349,47 @@  struct drm_amdgpu_gem_op {
 	/** GEM object handle */
 	__u32	handle;
 	/** AMDGPU_GEM_OP_* */
 	__u32	op;
 	/** Input or return value */
 	__u64	value;
 };
 
 #define AMDGPU_VA_OP_MAP			1
 #define AMDGPU_VA_OP_UNMAP			2
+#define AMDGPU_VA_OP_CLEAR			3
+#define AMDGPU_VA_OP_REPLACE			4
 
 /* Delay the page table update till the next CS */
 #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
 
 /* Mapping flags */
 /* readable mapping */
 #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
 /* writable mapping */
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
+/* partially resident texture */
+#define AMDGPU_VM_PAGE_PRT		(1 << 4)
+/* MTYPE flags use bit 5 to 8 */
+#define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
+/* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
+#define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
+/* Use NC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_NC		(1 << 5)
+/* Use WC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_WC		(2 << 5)
+/* Use CC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_CC		(3 << 5)
+/* Use UC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_UC		(4 << 5)
 
 struct drm_amdgpu_gem_va {
 	/** GEM object handle */
 	__u32 handle;
 	__u32 _pad;
 	/** AMDGPU_VA_OP_* */
 	__u32 operation;
 	/** AMDGPU_VM_PAGE_* */
 	__u32 flags;
 	/** va address to assign . Must be correctly aligned.*/
@@ -421,23 +438,26 @@  struct drm_amdgpu_cs_out {
 union drm_amdgpu_cs {
 	struct drm_amdgpu_cs_in in;
 	struct drm_amdgpu_cs_out out;
 };
 
 /* Specify flags to be used for IB */
 
 /* This IB should be submitted to CE */
 #define AMDGPU_IB_FLAG_CE	(1<<0)
 
-/* CE Preamble */
+/* Preamble flag, which means the IB could be dropped if no context switch */
 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 
+/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
+#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
+
 struct drm_amdgpu_cs_chunk_ib {
 	__u32 _pad;
 	/** AMDGPU_IB_FLAG_* */
 	__u32 flags;
 	/** Virtual address to begin IB execution */
 	__u64 va_start;
 	/** Size of submission */
 	__u32 ib_bytes;
 	/** HW IP to submit to */
 	__u32 ip_type;
@@ -499,20 +519,24 @@  struct drm_amdgpu_cs_chunk_data {
 	/* Subquery id: Query GFX CE firmware version */
 	#define AMDGPU_INFO_FW_GFX_CE		0x06
 	/* Subquery id: Query GFX RLC firmware version */
 	#define AMDGPU_INFO_FW_GFX_RLC		0x07
 	/* Subquery id: Query GFX MEC firmware version */
 	#define AMDGPU_INFO_FW_GFX_MEC		0x08
 	/* Subquery id: Query SMC firmware version */
 	#define AMDGPU_INFO_FW_SMC		0x0a
 	/* Subquery id: Query SDMA firmware version */
 	#define AMDGPU_INFO_FW_SDMA		0x0b
+	/* Subquery id: Query PSP SOS firmware version */
+	#define AMDGPU_INFO_FW_SOS		0x0c
+	/* Subquery id: Query PSP ASD firmware version */
+	#define AMDGPU_INFO_FW_ASD		0x0d
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
 /* the used VRAM size */
 #define AMDGPU_INFO_VRAM_USAGE			0x10
 /* the used GTT size */
 #define AMDGPU_INFO_GTT_USAGE			0x11
 /* Information about GDS, etc. resource configuration */
 #define AMDGPU_INFO_GDS_CONFIG			0x13
 /* Query information about VRAM and GTT domains */
 #define AMDGPU_INFO_VRAM_GTT			0x14
@@ -529,20 +553,36 @@  struct drm_amdgpu_cs_chunk_data {
 /* Query vce clock table */
 #define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
 /* Query vbios related information */
 #define AMDGPU_INFO_VBIOS			0x1B
 	/* Subquery id: Query vbios size */
 	#define AMDGPU_INFO_VBIOS_SIZE		0x1
 	/* Subquery id: Query vbios image */
 	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
 /* Query UVD handles */
 #define AMDGPU_INFO_NUM_HANDLES			0x1C
+/* Query sensor related information */
+#define AMDGPU_INFO_SENSOR			0x1D
+	/* Subquery id: Query GPU shader clock */
+	#define AMDGPU_INFO_SENSOR_GFX_SCLK		0x1
+	/* Subquery id: Query GPU memory clock */
+	#define AMDGPU_INFO_SENSOR_GFX_MCLK		0x2
+	/* Subquery id: Query GPU temperature */
+	#define AMDGPU_INFO_SENSOR_GPU_TEMP		0x3
+	/* Subquery id: Query GPU load */
+	#define AMDGPU_INFO_SENSOR_GPU_LOAD		0x4
+	/* Subquery id: Query average GPU power	*/
+	#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER	0x5
+	/* Subquery id: Query northbridge voltage */
+	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
+	/* Subquery id: Query graphics voltage */
+	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
 
 struct drm_amdgpu_query_fw {
 	/** AMDGPU_INFO_FW_* */
 	__u32 fw_type;
 	/**
@@ -592,20 +632,24 @@  struct drm_amdgpu_info {
 			/** For future use, no flags defined so far */
 			__u32 flags;
 		} read_mmr_reg;
 
 		struct drm_amdgpu_query_fw query_fw;
 
 		struct {
 			__u32 type;
 			__u32 offset;
 		} vbios_info;
+
+		struct {
+			__u32 type;
+		} sensor_info;
 	};
 };
 
 struct drm_amdgpu_info_gds {
 	/** GDS GFX partition size */
 	__u32 gds_gfx_partition_size;
 	/** GDS compute partition size */
 	__u32 compute_partition_size;
 	/** total GDS memory size */
 	__u32 gds_total_size;
@@ -703,20 +747,30 @@  struct drm_amdgpu_info_device {
 	__u32 pte_fragment_size;
 	__u32 gart_page_size;
 	/** constant engine ram size*/
 	__u32 ce_ram_size;
 	/** video memory type info*/
 	__u32 vram_type;
 	/** video memory bit width*/
 	__u32 vram_bit_width;
 	/* vce harvesting instance */
 	__u32 vce_harvest_config;
+	/* gfx double offchip LDS buffers */
+	__u32 gc_double_offchip_lds_buf;
+	/* NGG Primitive Buffer */
+	__u64 prim_buf_gpu_addr;
+	/* NGG Position Buffer */
+	__u64 pos_buf_gpu_addr;
+	/* NGG Control Sideband */
+	__u64 cntl_sb_buf_gpu_addr;
+	/* NGG Parameter Cache */
+	__u64 param_buf_gpu_addr;
 };
 
 struct drm_amdgpu_info_hw_ip {
 	/** Version of h/w IP */
 	__u32  hw_ip_version_major;
 	__u32  hw_ip_version_minor;
 	/** Capabilities */
 	__u64  capabilities_flags;
 	/** command buffer address start alignment*/
 	__u32  ib_start_alignment;