diff mbox

drm/amd/powerplay: fix a signedness bugs

Message ID 20170516144253.vvu3i6mbx3rv5uki@mwanda (mailing list archive)
State New, archived
Headers show

Commit Message

Dan Carpenter May 16, 2017, 2:42 p.m. UTC 
Smatch complains about a signedness bug here:

	vega10_hwmgr.c:4202 vega10_force_clock_level()
	warn: always true condition '(i >= 0) => (0-u32max >= 0)'

Fixes: 7b52db39a4c2 ("drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>

Comments

Eric Huang May 18, 2017, 4:28 p.m. UTC | #1 
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>


On 2017-05-16 10:42 AM, Dan Carpenter wrote:
> Smatch complains about a signedness bug here:
>
> 	vega10_hwmgr.c:4202 vega10_force_clock_level()
> 	warn: always true condition '(i >= 0) => (0-u32max >= 0)'
>
> Fixes: 7b52db39a4c2 ("drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.")
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index ad30f5d3a10d..2614af2f553f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4186,7 +4186,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
>   		enum pp_clock_type type, uint32_t mask)
>   {
>   	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
> -	uint32_t i;
> +	int i;
>   
>   	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
>   		return -EINVAL;
Zhu, Rex May 23, 2017, 5:36 a.m. UTC | #2 
Patches has been applied.


Thanks.


Best Regards

Rex
diff mbox

Patch

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ad30f5d3a10d..2614af2f553f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4186,7 +4186,7 @@  static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask)
 {
 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
-	uint32_t i;
+	int i;
 
 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
 		return -EINVAL;