From patchwork Wed Jul 19 17:39:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 9852897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 12A68602BD for ; Wed, 19 Jul 2017 17:40:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 073B9286C0 for ; Wed, 19 Jul 2017 17:40:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F0840286D9; Wed, 19 Jul 2017 17:40:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DCDE2286C0 for ; Wed, 19 Jul 2017 17:40:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D82E6E578; Wed, 19 Jul 2017 17:39:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pg0-f47.google.com (mail-pg0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBC606E573 for ; Wed, 19 Jul 2017 17:39:57 +0000 (UTC) Received: by mail-pg0-f47.google.com with SMTP id k14so3280901pgr.0 for ; Wed, 19 Jul 2017 10:39:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6SQD8CU06GpEoX2ewCl73AfC5k7uvqOnNDaCSQIuonQ=; b=Sk7Y31x/FudSyyW9tJZrwIIoML6HdHaDeBCGmK3KM3Qop3O6T4z49fIrt2+2tHUVy+ bY/h14kSYbFmn9DUzBOsr7gvjUa+mODzB2NjXaqsuhAo3WR6ikX7LXex+xfNOCspXGI4 okJFcIeHPgL0SBtZPyTTnOJ/kuopgqdaPQ+oBR648a9jE8gZr8ZYZG7bkPIyDOWlLTAH 5fsSxgSt7Gt14RNtKLkDM0rSQ6t/P4+om6+xOE1YM0hd2JzyiMiolb0gVnbKJJgoJNYZ ZtQFKN2OqT+6fK1Z/0w3H5A+r6EsXQQSL1vN8FjhZOTYr2LsLLLxwcoO0tjC/CocL/uM a7Mg== X-Gm-Message-State: AIVw111lnAgynQAhpYJBwpMyEgr1rDfnSB1PJR93XPQt8ZMYJjE1IJA7 VtKlD5phN918Ea67 X-Received: by 10.99.146.67 with SMTP id s3mr903609pgn.130.1500485997306; Wed, 19 Jul 2017 10:39:57 -0700 (PDT) Received: from mka.mtv.corp.google.com ([172.22.64.162]) by smtp.gmail.com with ESMTPSA id o14sm811205pfi.158.2017.07.19.10.39.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Jul 2017 10:39:56 -0700 (PDT) From: Matthias Kaehlcke To: Daniel Vetter , Jani Nikula , David Airlie , Daniel Vetter Subject: [PATCH] drm/i915: Pass enum pipe to intel_set_pch_fifo_underrun_reporting() Date: Wed, 19 Jul 2017 10:39:28 -0700 Message-Id: <20170719173928.186638-1-mka@chromium.org> X-Mailer: git-send-email 2.14.0.rc0.284.gd933b75aa4-goog Cc: Grant Grundler , intel-gfx , Linux Kernel Mailing List , dri-devel@lists.freedesktop.org, Matthias Kaehlcke X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Commit a21960339c8c ("drm/i915: Consistently use enum pipe for PCH transcoders") misses some pieces, due to a problem with the patch format, this patch adds the remaining bits. Fixes: a21960339c8c ("drm/i915: Consistently use enum pipe for PCH transcoders") Signed-off-by: Matthias Kaehlcke --- drivers/gpu/drm/i915/intel_display.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a89d0fd1c2e1..5c7054c3be0e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5347,8 +5347,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, return; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); @@ -5433,8 +5432,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, intel_wait_for_vblank(dev_priv, pipe); intel_wait_for_vblank(dev_priv, pipe); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } /* If we change the relative order between pipe/planes enabling, we need @@ -5531,8 +5529,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -5560,8 +5557,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_disable(crtc, old_crtc_state, old_state); if (old_crtc_state->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } static void i9xx_pfit_enable(struct intel_crtc *crtc)