From patchwork Thu Sep 7 12:49:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9942219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 491506035F for ; Thu, 7 Sep 2017 12:49:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DC59285B5 for ; Thu, 7 Sep 2017 12:49:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 22A8B285EA; Thu, 7 Sep 2017 12:49:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C9D59285B5 for ; Thu, 7 Sep 2017 12:49:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 840316E92D; Thu, 7 Sep 2017 12:49:46 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x231.google.com (mail-lf0-x231.google.com [IPv6:2a00:1450:4010:c07::231]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CEE36E92B for ; Thu, 7 Sep 2017 12:49:45 +0000 (UTC) Received: by mail-lf0-x231.google.com with SMTP id d17so24298880lfe.2 for ; Thu, 07 Sep 2017 05:49:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DBMFn9eaNq+TiYu1K2GplSGQcy0o0Nf1R50LQopOPzY=; b=gB8z4kQNz03ZapJO49LvAF4kiSbjYW9QUuagfoN171WFPJZeFbEE9PPTr5+jrXS8Cy sFkR4no3XCM5KA/gsKdwvtgo/p27dJnq22p0vkg/+U4xMBksq1FYJHLjWpLuW/O/hIuK pilkYtO9UyxKwAI6W6emGn4+LpjBwgRNrDptk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DBMFn9eaNq+TiYu1K2GplSGQcy0o0Nf1R50LQopOPzY=; b=rch6aHn8NANSYAVTh7QzGSrykLTQQXJEj6GGJOztb9gdB+3trw5nld6DM9e/o1xHAm 6vO3XI284zBZd3JqyeFHxiR6OGK1aZSMN1HqySczGp6MG9aUTfyIquQEVdYY06HrXm0y 7uZ5ob55UXJ+ESxw+jCCfxPCenLUfzkDAG+Fgu99dvFy6pn97B2JvJowofNH9T2ftozt 7dVAsxTf1PZ1P+7VI4CmE4GKLUnlfDBxiSAjyA+oOQR0t27gxt5YfxFFwsdp8Yz5U9wQ 4BNnnrVow1e3NekNydfNzJrdzj83ScnMU9Ayk8tamWihOzVehLfaXHzXlSqlN4SM1BDx R2vg== X-Gm-Message-State: AHPjjUhWzZZkmMvbXnGUNzFxi8ivprSEvrJyQcoeXdGGActLwpVZTSK4 2Iwvl/kMChGuEZme X-Google-Smtp-Source: ADKCNb5wWnEzXCSO1pK1kjK2V8qXhvXh7wLZWf75HDekbtl1o/PQkrpLuyEW//+m1i6drUlwl96Ysg== X-Received: by 10.46.68.154 with SMTP id b26mr948907ljf.159.1504788583794; Thu, 07 Sep 2017 05:49:43 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id g65sm405841ljb.86.2017.09.07.05.49.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 05:49:43 -0700 (PDT) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt Subject: [PATCH 5/7 v3] drm/pl111: Insert delay before powering up PL11x Date: Thu, 7 Sep 2017 14:49:23 +0200 Message-Id: <20170907124925.13805-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907124925.13805-1-linus.walleij@linaro.org> References: <20170907124925.13805-1-linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The old codebase has a delay between enabling and powering up the PL11x. According to the manual for PL110, ARM DDI 0161E page 1-5 and the PL111 manual ARM DDI 0293C page 1-6, the power sequence should be such that once Vdd is stable (which we assume it is at boot) LCDEN is enabled first and then CLPOWER should be enabled "after the signals have stabilized" and this is said to be display-dependent. The old codebase uses 20ms. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Rebase on DRM-TIP ChangeLog v1->v2: - Fall back to the delay of 20 ms from the old framebuffer driver to stabilize Vee in shortage of other alternatives. --- drivers/gpu/drm/pl111/pl111_display.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index b104011cea55..b7df9f5df881 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -155,8 +155,8 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, writel(0, priv->regs + CLCD_TIM3); - /* Enable and Power Up */ - cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDPWR | CNTL_LCDVCOMP(1); + /* Hard-code TFT panel */ + cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); /* Note that the the hardware's format reader takes 'r' from * the low bit, while DRM formats list channels from high bit @@ -199,6 +199,17 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, break; } + /* Power sequence: first enable and chill */ + writel(cntl, priv->regs + priv->ctrl); + + /* + * We expect this delay to stabilize the contrast + * voltage Vee as stipulated by the manual + */ + msleep(20); + + /* Power Up */ + cntl |= CNTL_LCDPWR; writel(cntl, priv->regs + priv->ctrl); drm_crtc_vblank_on(crtc); @@ -209,10 +220,24 @@ void pl111_display_disable(struct drm_simple_display_pipe *pipe) struct drm_crtc *crtc = &pipe->crtc; struct drm_device *drm = crtc->dev; struct pl111_drm_dev_private *priv = drm->dev_private; + u32 cntl; drm_crtc_vblank_off(crtc); - /* Disable and Power Down */ + /* Power Down */ + cntl = readl(priv->regs + priv->ctrl); + if (cntl & CNTL_LCDPWR) { + cntl &= ~CNTL_LCDPWR; + writel(cntl, priv->regs + priv->ctrl); + } + + /* + * We expect this delay to stabilize the contrast voltage Vee as + * stipulated by the manual + */ + msleep(20); + + /* Disable */ writel(0, priv->regs + priv->ctrl); clk_disable_unprepare(priv->clk);