From patchwork Wed Oct 18 13:58:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 10014741 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA71E60211 for ; Wed, 18 Oct 2017 13:58:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BFB8928B68 for ; Wed, 18 Oct 2017 13:58:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B44A028B6B; Wed, 18 Oct 2017 13:58:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6519528B68 for ; Wed, 18 Oct 2017 13:58:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 713326E8CA; Wed, 18 Oct 2017 13:58:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 030D46E8C3; Wed, 18 Oct 2017 13:58:30 +0000 (UTC) Received: by mail-wr0-x244.google.com with SMTP id l1so5135449wrc.3; Wed, 18 Oct 2017 06:58:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9mvetThlt4alMNH2P1jGl+Iqkca52CLGF1BzPx+T6Ls=; b=g7tz3xesJblB3GRldwJBVAvBE7EJZAJZziegoshk8gblFUKRCYbfWFLCCO8dD+qWZd cHF8a2gfVNrGZHUfCayWwiQH6WUs2SgB8E43pvV+nd2A86hC8sNi+0ltOvwbEzjL/kFB yzizSu3/6rZPwGmLyfTy/wQRz0v/kJ2YhKZNNPMyt1X2O5pZw8RqPef3/+DCckf3WopV lgvSjYt1cca46kAUY5k5cXipcr1ShdF56G0D0EaureLvvlQ/UgsjHc5bTN3E6bcydP5h J1j63kMol51Ybru2Z2lUyTX+J2WG84mGU34JuI6gVhybniagYLRQWoKs5usao10Uq2mZ GlHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9mvetThlt4alMNH2P1jGl+Iqkca52CLGF1BzPx+T6Ls=; b=OHrSZS9oYFbl1SKP6HGEix3Le4q8u/DGS2cFqI4dp23Zj6Ve6JG6ja+DOlinKwcgzh XT6AhhVhTZ7DaYpN3L/MXQQQ2Z9P6y20klBabT0x+vzq8ltbTwUlpzsjBUc5i05QrZVy n08QPWVW0XmAm/u1SRW1ZUqLhKeT4jHRoszyYNZEzGc72a5/HzZNm7CJMy4v4Erd+LUQ DomCtROnWo3ntSqmlHO+Vfpukm2ipxCnVhNNeYHOV/F1HmA1pCGG1PyuReYbwyZsCQce fIT7N9eOPEm/uMQCdCrVMOdpLjzZgLt5cQHRnIZuqbxsZRaOpEAk1An0sHmYsEChIlVT oYrA== X-Gm-Message-State: AMCzsaW652KmCP8yBUPsThUwEzgJKHHWfaAoAXKZg9edvynlJqKw9JWc 2qNkCVVushVz3r6RRlpKShg= X-Google-Smtp-Source: ABhQp+QlIyxbvMbnCGe5D11+KvX1kffSQltQC9UTYtZZAzYFjZSZzlQ27V7cNyEvIM2ESmOeagO+WA== X-Received: by 10.223.182.19 with SMTP id f19mr7376777wre.166.1508335109498; Wed, 18 Oct 2017 06:58:29 -0700 (PDT) Received: from localhost.localdomain ([2a02:908:1251:7981:4537:45bc:69b6:7f1e]) by smtp.gmail.com with ESMTPSA id o24sm15780699wmi.39.2017.10.18.06.58.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Oct 2017 06:58:29 -0700 (PDT) From: "=?UTF-8?q?Christian=20K=C3=B6nig?=" X-Google-Original-From: =?UTF-8?q?Christian=20K=C3=B6nig?= To: helgaas@kernel.org, linux-pci@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v9 4/5] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v5 Date: Wed, 18 Oct 2017 15:58:20 +0200 Message-Id: <20171018135821.3248-5-deathsimple@vodafone.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171018135821.3248-1-deathsimple@vodafone.de> References: <20171018135821.3248-1-deathsimple@vodafone.de> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Christian König Most BIOS don't enable this because of compatibility reasons. Manually enable a 64bit BAR of 64GB size so that we have enough room for PCI devices. v2: style cleanups, increase size, add resource name, set correct flags, print message that windows was added v3: add defines for all the magic numbers, style cleanups v4: add some comment that the BIOS should actually allow this using _PRS and _SRS. v5: only enable this if CONFIG_PHYS_ADDR_T_64BIT is set Signed-off-by: Christian König Reviewed-by: Andy Shevchenko --- arch/x86/pci/fixup.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 11e407489db0..7b6bd76713c5 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -618,3 +618,83 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) + +/* + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow + * configuring host bridge windows using the _PRS and _SRS methods. + * + * But this is rarely implemented, so we manually enable a large 64bit BAR for + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. + */ +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) +{ + struct resource *res, *conflict; + u32 base, limit, high; + unsigned i; + + for (i = 0; i < 8; ++i) { + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); + + /* Is this slot free? */ + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | + AMD_141b_MMIO_BASE_WE_MASK))) + break; + + base >>= 8; + base |= high << 24; + + /* Abort if a slot already configures a 64bit BAR. */ + if (base > 0x10000) + return; + } + if (i == 8) + return; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->name = "PCI Bus 0000:00"; + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; + res->start = 0x100000000ull; + res->end = 0xfd00000000ull - 1; + + /* Just grab the free area behind system memory for this */ + while ((conflict = request_resource_conflict(&iomem_resource, res))) + res->start = conflict->end + 1; + + dev_info(&dev->dev, "adding root bus resource %pR\n", res); + + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); + + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); + + pci_bus_add_resource(dev->bus, res, 0); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); + +#endif