From patchwork Fri Oct 27 15:06:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10032197 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1B2AC6039A for ; Mon, 30 Oct 2017 08:17:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0ADBF285CE for ; Mon, 30 Oct 2017 08:17:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F3A282874A; Mon, 30 Oct 2017 08:17:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 016C1285CE for ; Mon, 30 Oct 2017 08:17:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04575899DB; Mon, 30 Oct 2017 08:17:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from dwarf.birch.relay.mailchannels.net (dwarf.birch.relay.mailchannels.net [23.83.209.53]) by gabe.freedesktop.org (Postfix) with ESMTPS id 265126E970 for ; Fri, 27 Oct 2017 15:10:11 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 627437C9122; Fri, 27 Oct 2017 15:10:10 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.143.180]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id 85A327C9A23; Fri, 27 Oct 2017 15:10:09 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.20.63.14]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.9.14); Fri, 27 Oct 2017 15:10:10 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Soft-Wiry: 16c9da4b756410ac_1509117010128_243910038 X-MC-Loop-Signature: 1509117010128:1628945043 X-MC-Ingress-Time: 1509117010128 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id AF0E24C215; Fri, 27 Oct 2017 15:10:04 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Rob Herring Subject: [PATCH v2 08/10] dt-bindings: add binding for A64 DE2 CCU SRAM Date: Fri, 27 Oct 2017 23:06:56 +0800 Message-Id: <20171027150658.18509-9-icenowy@aosc.io> In-Reply-To: <20171027150658.18509-1-icenowy@aosc.io> References: <20171027150658.18509-1-icenowy@aosc.io> X-Mailman-Approved-At: Mon, 30 Oct 2017 08:17:31 +0000 Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed, otherwise the whole DE2 memory zone cannot be accessed (kept to all 0). Add binding for this, in order to make the DE2 CCU able to claim the SRAM and enable access to the DE2 clock and reset registers. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring --- Changes in v2: - Adds description of the situation when the SRAM is not claimed. Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index f2fa87c4765c..a7d558a2b9b2 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -6,6 +6,7 @@ Required properties : - "allwinner,sun8i-a83t-de2-clk" - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" + - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length @@ -18,6 +19,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +Additional required properties for "allwinner,sun50i-a64-de2-clk" : +- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt, + should be the SRAM C section on A64 SoC. + Example: de2_clocks: clock@1000000 { compatible = "allwinner,sun8i-h3-de2-clk";