From patchwork Tue Nov 14 12:47:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10057523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A2BC860231 for ; Tue, 14 Nov 2017 12:47:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4FBD296F1 for ; Tue, 14 Nov 2017 12:47:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9EBC29746; Tue, 14 Nov 2017 12:47:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 50966296F1 for ; Tue, 14 Nov 2017 12:47:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 270B489CFA; Tue, 14 Nov 2017 12:47:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F21189E32 for ; Tue, 14 Nov 2017 12:47:29 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vAEClPPP029521; Tue, 14 Nov 2017 06:47:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1510663646; bh=k3XZcs27qYGscE1yx6fZhtZUNzvXx9pnLYtEs/Jisps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eW1Fhu5rV7q97xhtPL0YySYiOBhTCWteMPuRi0q2Pi2d911AvAjgrBjeXxtkrPNHX MnieAkXrqXk+0UAtkloBeYbI4X8zmYBseV3FtiV2bWIvbdjqZ4AVD78wLalBu0yNBj I2WzkuYTJVsvUq3TpdlD3LmuiT8PbJ7Nu8jTOPBY= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vAEClPUU005876; Tue, 14 Nov 2017 06:47:25 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 14 Nov 2017 06:47:25 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 14 Nov 2017 06:47:25 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vAEClGxa006647; Tue, 14 Nov 2017 06:47:23 -0600 From: Peter Ujfalusi To: , Subject: [PATCH v2 3/3] drm/omap: Filter displays mode based on bandwidth limit Date: Tue, 14 Nov 2017 14:47:55 +0200 Message-ID: <20171114124755.14277-4-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171114124755.14277-1-peter.ujfalusi@ti.com> References: <20171114124755.14277-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: airlied@linux.ie, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP If we have memory bandwidth limit configured, reject the modes which would require more bandwidth than the limit if it is used with one full resolution plane (most common use case). This filtering is not providing full protection as it is possible that application would pick smaller crtc resolution with high resolution planes and down scaling, or can enable more smaller planes where the sum of their bandwidth need would be higher than the limit. This patch only allows us to filter out modes which would need more bandwidth if they were used with one full screen plane. Signed-off-by: Peter Ujfalusi --- drivers/gpu/drm/omapdrm/omap_crtc.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/omapdrm/omap_drv.c | 5 +++++ drivers/gpu/drm/omapdrm/omap_drv.h | 3 +++ 3 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index cc85c16cbc2a..ae2e16ed3874 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "omap_drv.h" @@ -400,6 +401,41 @@ static void omap_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); } +static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct omap_drm_private *priv = crtc->dev->dev_private; + + /* Check for bandwidth limit */ + if (priv->max_bandwidth) { + /* + * Estimation for the bandwidth need of a given mode with one + * full screen plane: + * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) + * ^^ Refresh rate ^^ + * + * The interlaced mode is taken into account by using the + * pixelclock in the calculation. + * + * The equation is rearranged for 64bit arithmetic. + */ + uint64_t bandwidth = mode->clock * 1000; + unsigned int bpp = 4; + + bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; + bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); + + /* + * Reject modes which would need more bandwidth if used with one + * full resolution plane (most common use case). + */ + if (priv->max_bandwidth < bandwidth) + return MODE_BAD; + } + + return MODE_OK; +} + static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); @@ -621,6 +657,7 @@ static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { .atomic_flush = omap_crtc_atomic_flush, .atomic_enable = omap_crtc_atomic_enable, .atomic_disable = omap_crtc_atomic_disable, + .mode_valid = omap_crtc_mode_valid, }; /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 528cf5c25bec..58b4a0e149e0 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -701,6 +701,11 @@ static int pdev_probe(struct platform_device *pdev) spin_lock_init(&priv->list_lock); INIT_LIST_HEAD(&priv->obj_list); + /* Get memory bandwidth limits */ + if (priv->dispc_ops->get_memory_bandwidth_limit) + priv->max_bandwidth = + priv->dispc_ops->get_memory_bandwidth_limit(); + omap_gem_init(ddev); ret = omap_modeset_init(ddev); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index cccaae787a7c..d49715272080 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -86,6 +86,9 @@ struct omap_drm_private { spinlock_t wait_lock; /* protects the wait_list */ struct list_head wait_list; /* list of omap_irq_wait */ uint32_t irq_mask; /* enabled irqs in addition to wait_list */ + + /* memory bandwidth limit if it is needed on the platform */ + unsigned int max_bandwidth; };