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[2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id 78sm12496734qkb.51.2017.12.20.10.15.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Dec 2017 10:15:22 -0800 (PST) Date: Wed, 20 Dec 2017 19:15:20 +0100 From: Thierry Reding To: Guillaume Tucker Subject: Re: [RFC PATCH v2 1/1] drm/tegra: sor: Fix hang on tegra124 due to NULL clk_out Message-ID: <20171220181520.GA9687@ulmo> References: <0f776b7500ee0e74b316b9803803b309779d2ff7.1513768618.git.guillaume.tucker@collabora.com> MIME-Version: 1.0 In-Reply-To: <0f776b7500ee0e74b316b9803803b309779d2ff7.1513768618.git.guillaume.tucker@collabora.com> User-Agent: Mutt/1.9.1 (2017-09-22) Cc: David Airlie , Peter De Schrijver , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Jon Hunter , linux-tegra@vger.kernel.org, Thierry Reding X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Wed, Dec 20, 2017 at 11:32:23AM +0000, Guillaume Tucker wrote: > When neither HDMI nor DP is supported such as on the tegra124, the > sor->clk_out is not initialised and remains NULL. In this case, the > parent clock can't be assigned to it so revert to the previous > behaviour of assigning it to the main sor->clk instead. > > This fixes a kernel hang on tegra124 and should also affect tegra210 > as they both don't support HDMI and DP. Tested on tegra124 only. > > Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") > Signed-off-by: Guillaume Tucker > CC: Thierry Reding > --- > drivers/gpu/drm/tegra/sor.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) How about just the below instead? It's one more line than your patch, but it will automatically handle all occurrences of clk_out properly. --- >8 --- diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index f6313c4d612e..4be9edf9c6fe 100644 That said, I suspect the SOR might be compatible from a clock point of view with later versions and perhaps we just didn't implement clocks correctly back in the Tegra124 timeframe. Maybe Peter knows. Thierry Tested-by: Jon Hunter --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3047,6 +3047,8 @@ static int tegra_sor_probe(struct platform_device *pdev) name, err); goto remove; } + } else { + sor->clk_out = sor->clk; } sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); --- >8 ---