From patchwork Thu Jan 11 16:54:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10158247 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 394D9605BA for ; Thu, 11 Jan 2018 17:01:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 199632883C for ; Thu, 11 Jan 2018 17:01:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1836828870; Thu, 11 Jan 2018 17:01:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7C1D9288D1 for ; Thu, 11 Jan 2018 17:01:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68AD26E7C0; Thu, 11 Jan 2018 17:01:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6055F6E7C0 for ; Thu, 11 Jan 2018 17:01:01 +0000 (UTC) Received: by mail-lf0-x244.google.com with SMTP id m8so3554067lfc.6 for ; Thu, 11 Jan 2018 09:01:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:message-id:user-agent:date:to:to:to:to:cc:subject:mime-version :content-disposition; bh=4AAORx4kiaJ3YQdV5dH7HQklxZyAbefZii5tdVIQLFM=; b=k5AWjL581W5PvnByCMPG9fpO1QBCkqCZDBXIkVbESZ4ak4Lj0aJ3v2YFmKil8Woy77 vVVH+hd2sKYXGJ5iGVNLBPkcanouHyBqbyQ5edIBMn/BVYoZen8tZ6C+bhp28/0LQ4lC zCv1F5rUPvRkcvZh2cvNO4IFbzEFYed/sJRiNX1fnGNxMGF0AF9Cv2M2egKP8pT8UPuv lZnnL1S/dsvtjPVSadT/rSERXd1+IknTlE2ZxawWHeym55rcxZlz1ayR4RlpSTVukFVH vl5xJIRq2qqBH/sxHMgRsBvdhlv35Ti4ZD2G4tPLiEyah3Qexs6ulSxGQgfjtbS7026Q JaBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:message-id:user-agent:date:to:to:to:to:cc :subject:mime-version:content-disposition; bh=4AAORx4kiaJ3YQdV5dH7HQklxZyAbefZii5tdVIQLFM=; b=OQGQhsW+zEfpxMozqKsnu0IYk3KvrNsrsP5c8VVXpRH9Q9xxdpzwmSVZBzoke8s0mY V1t7rgQV+NyfoRX6XUawDpBhHgrI1rJDbHxsrdKIboCBvHttU3HrmUXCHOA2vWAqw8zN /G7F31f1loR9fubXQOVfkI3BabPaQQgdNhsPf4kCKfq+tb7zp2Q43H0s6JZBXwfDC6Nu xTpEAk6ZT5BfQdvo9Af8CJ12LxubVgZp1oXF8oYrpTayj08xBC9TmFdeyAhpYVeHKVON QKmyobO0nN5rXXt0CMEFyiUhVzVYnmJETvohBJBSVaiwf42gxGUgJMhrEMBr+cKkswjh yq2g== X-Gm-Message-State: AKGB3mIFsoxFDBhg4y6OVg212fMisM8MvU+6BzfN9kd//XsLT6MjVqhW 3GRLHYIQSQuo1EG5ij3h1nu9fQ== X-Google-Smtp-Source: ACJfBot3wNCQweWEqQInmrOuQgRSljyZ1DCv2s7J+0lTOLCzxi8toOknLobuJndKkUXrbYlnN6qRzQ== X-Received: by 10.46.60.15 with SMTP id j15mr15051406lja.38.1515690059500; Thu, 11 Jan 2018 09:00:59 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.85.218]) by smtp.gmail.com with ESMTPSA id a71sm3952793ljf.6.2018.01.11.09.00.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 09:00:58 -0800 (PST) From: Sergei Shtylyov X-Google-Original-From: "Sergei Shtylyov" Received: by wasted.cogentembedded.com (sSMTP sendmail emulation); Thu, 11 Jan 2018 20:00:55 +0300 Message-Id: <20180111170055.878913975@cogentembedded.com> User-Agent: quilt/0.64 Date: Thu, 11 Jan 2018 19:54:33 +0300 To: Laurent Pinchart , David Airlie , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org To: Rob Herring To: Mark Rutland To: devicetree@vger.kernel.org Subject: [PATCH 1/3] drm: rcar-du: lvds: refactor LVDS startup MIME-Version: 1.0 Content-Disposition: inline; filename=drm-rcar-du-lvds-refactor-LVDS-startup.patch Cc: Sergei Shtylyov X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP After the recent correction of the R-Car gen3 LVDCR1 value, already similar enough at their ends rcar_du_lvdsenc_start_gen{2|3}() started asking for a merge and it's becoming actually necessary with the addition the R-Car V3M (R8A77970) support -- this gen3 SoC has gen2-like LVDPLLCR layout. BTW, such a merge saves 72 bytes of the object code with AArch64 gcc 4.8.5. Signed-off-by: Sergei Shtylyov --- drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 132 ++++++++++++------------------ 1 file changed, 54 insertions(+), 78 deletions(-) Index: linux/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c =================================================================== --- linux.orig/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ linux/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c @@ -39,98 +39,41 @@ static void rcar_lvds_write(struct rcar_ iowrite32(data, lvds->mmio + reg); } -static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds, - struct rcar_du_crtc *rcrtc) +static u32 rcar_lvds_gen2_lvdpllcr(unsigned int freq) { - const struct drm_display_mode *mode = &rcrtc->crtc.mode; - unsigned int freq = mode->clock; - u32 lvdcr0; - u32 pllcr; + u32 lvdpllcr; - /* PLL clock configuration */ if (freq < 39000) - pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M; + lvdpllcr = LVDPLLCR_PLLDLYCNT_38M; else if (freq < 61000) - pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M; + lvdpllcr = LVDPLLCR_PLLDLYCNT_60M; else if (freq < 121000) - pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M; + lvdpllcr = LVDPLLCR_PLLDLYCNT_121M; else - pllcr = LVDPLLCR_PLLDLYCNT_150M; - - rcar_lvds_write(lvds, LVDPLLCR, pllcr); - - /* - * Select the input, hardcode mode 0, enable LVDS operation and turn - * bias circuitry on. - */ - lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN; - if (rcrtc->index == 2) - lvdcr0 |= LVDCR0_DUSEL; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); + return LVDPLLCR_PLLDLYCNT_150M; - /* Turn all the channels on. */ - rcar_lvds_write(lvds, LVDCR1, - LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | - LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY); - - /* - * Turn the PLL on, wait for the startup delay, and turn the output - * on. - */ - lvdcr0 |= LVDCR0_PLLON; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); - - usleep_range(100, 150); - - lvdcr0 |= LVDCR0_LVRES; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); + return lvdpllcr | LVDPLLCR_CEEN | LVDPLLCR_COSEL; } -static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, - struct rcar_du_crtc *rcrtc) +static u32 rcar_lvds_gen3_lvdpllcr(unsigned int freq) { - const struct drm_display_mode *mode = &rcrtc->crtc.mode; - unsigned int freq = mode->clock; - u32 lvdcr0; - u32 pllcr; - - /* PLL clock configuration */ if (freq < 42000) - pllcr = LVDPLLCR_PLLDIVCNT_42M; + return LVDPLLCR_PLLDIVCNT_42M; else if (freq < 85000) - pllcr = LVDPLLCR_PLLDIVCNT_85M; + return LVDPLLCR_PLLDIVCNT_85M; else if (freq < 128000) - pllcr = LVDPLLCR_PLLDIVCNT_128M; - else - pllcr = LVDPLLCR_PLLDIVCNT_148M; - - rcar_lvds_write(lvds, LVDPLLCR, pllcr); - - /* Turn all the channels on. */ - rcar_lvds_write(lvds, LVDCR1, - LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | - LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY); - - /* - * Turn the PLL on, set it to LVDS normal mode, wait for the startup - * delay and turn the output on. - */ - lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); - - lvdcr0 |= LVDCR0_PWD; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); + return LVDPLLCR_PLLDIVCNT_128M; - usleep_range(100, 150); - - lvdcr0 |= LVDCR0_LVRES; - rcar_lvds_write(lvds, LVDCR0, lvdcr0); + return LVDPLLCR_PLLDIVCNT_148M; } static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds, struct rcar_du_crtc *rcrtc) { - u32 lvdhcr; + u32 lvdhcr, lvdpllcr, lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT; + const struct drm_display_mode *mode = &rcrtc->crtc.mode; + unsigned int gen = lvds->dev->info->gen; + unsigned int freq = mode->clock; int ret; if (lvds->enabled) @@ -158,14 +101,47 @@ static int rcar_du_lvdsenc_start(struct else lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1) | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3); - rcar_lvds_write(lvds, LVDCHCR, lvdhcr); - /* Perform generation-specific initialization. */ - if (lvds->dev->info->gen < 3) - rcar_du_lvdsenc_start_gen2(lvds, rcrtc); + /* PLL clock configuration */ + if (gen < 3) + lvdpllcr = rcar_lvds_gen2_lvdpllcr(freq); else - rcar_du_lvdsenc_start_gen3(lvds, rcrtc); + lvdpllcr = rcar_lvds_gen3_lvdpllcr(freq); + rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr); + + if (gen < 3) { + /* + * Select the input, enable LVDS operation, and turn + * the bias circuitry on. + */ + lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN; + if (rcrtc->index == 2) + lvdcr0 |= LVDCR0_DUSEL; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + /* Turn all the channels on. */ + rcar_lvds_write(lvds, LVDCR1, + LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | + LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY); + + /* Turn the PLL on. */ + lvdcr0 |= LVDCR0_PLLON; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + + if (gen > 2) { + /* Turn on the LVDS normal mode. */ + lvdcr0 |= LVDCR0_PWD; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + /* Wait for the startup delay. */ + usleep_range(100, 150); + + /* Turn the output on. */ + lvdcr0 |= LVDCR0_LVRES; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds->enabled = true;