@@ -361,6 +361,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
link->max_lanes = 0;
drm_dp_link_caps_reset(&link->caps);
+ link->aux_rd_interval = 0;
link->edp = 0;
link->rate = 0;
@@ -414,6 +415,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
link->edp = edp_revs[value];
}
+ link->aux_rd_interval = drm_dp_aux_rd_interval(values);
+
link->rate = link->max_rate;
link->lanes = link->max_lanes;
@@ -997,6 +997,22 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_ALTERNATE_SCRAMBLER_RESET_CAP;
}
+/**
+ * drm_dp_read_aux_interval() - read the AUX read interval from the DPCD
+ * @dpcd: receiver capacity buffer
+ *
+ * Reads the AUX read interval (in microseconds) from the DPCD. Note that the
+ * TRAINING_AUX_RD_INTERVAL stores the value in units of 4 milliseconds.
+ *
+ * Returns:
+ * The read AUX interval in microseconds.
+ */
+static inline unsigned int
+drm_dp_aux_rd_interval(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4000;
+}
+
/*
* DisplayPort AUX channel
*/
@@ -1146,6 +1162,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
* @max_rate: maximum clock rate supported on the link
* @max_lanes: maximum number of lanes supported on the link
* @caps: capabilities supported on the link (see &drm_dp_link_caps)
+ * @aux_rd_interval: AUX read interval to use for training (in microseconds)
* @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
* @rate: currently configured link rate
* @lanes: currently configured number of lanes
@@ -1156,6 +1173,7 @@ struct drm_dp_link {
unsigned int max_lanes;
struct drm_dp_link_caps caps;
+ unsigned int aux_rd_interval;
unsigned char edp;
unsigned int rate;