From patchwork Wed Feb 7 18:58:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10205857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9035E602D8 for ; Wed, 7 Feb 2018 18:59:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72CE6290AA for ; Wed, 7 Feb 2018 18:59:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 66E9B290B8; Wed, 7 Feb 2018 18:59:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E78D3290AA for ; Wed, 7 Feb 2018 18:59:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B3936E39B; Wed, 7 Feb 2018 18:59:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-it0-f68.google.com (mail-it0-f68.google.com [209.85.214.68]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDB176E3B4 for ; Wed, 7 Feb 2018 18:59:31 +0000 (UTC) Received: by mail-it0-f68.google.com with SMTP id j21-v6so15630301ita.1 for ; Wed, 07 Feb 2018 10:59:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Nued7kf91GeqGnolnqC2Jecl+uL54xtx8eYf4/ACM7E=; b=eX1Fs/XLLBSfHxHcrqhvSBHpkg6N9HKVyL6AaTsGY9KTD0rbZw+X3jyqvtHQa0tSLu QsoDPBLOUHMmmNcrnsUyFeAw0QjlEB4drZiqaAGVUohGnioEDygaCGB+sSnuh1ljytrt dhNkcFbS+QdXlGYwPSP1BpeNR3QhVaj5v1zNTuicbRX/Xy+CQkEbrrlYoAoxRMCD7uUc vussBFS9ZBgbd6qCnn3/cvW3kw+bUIa3DEs/VJI3BpcfDF4RW1e6Xsc7xOGykOfbZMbd a/WalzW+vlsjPL8CbG2o6Lcq8BW88Ij4swH6iirh1GkYRSgPlVQdg6NfzuHN2e9tRO6T zRaQ== X-Gm-Message-State: APf1xPA6+X4yO/k2fW8KwBvpp8vGrZ6PAf1s2Eni0buKg8I7yHdP4/9E WH4+xurYLG7P38ymSU2wkKDWGg== X-Google-Smtp-Source: AH8x226y0A5XOga+zImBL06stLfWch8m8a6IAEx/rKBShuAZ2ffs7FnFsorpyfio7dUevspzrtqc2g== X-Received: by 10.36.39.215 with SMTP id g206mr8979019ita.17.1518029970654; Wed, 07 Feb 2018 10:59:30 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:0:1000:1600:5ff4:666d:2881:a60]) by smtp.gmail.com with ESMTPSA id w125sm2628637itb.31.2018.02.07.10.59.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Feb 2018 10:59:29 -0800 (PST) From: Matthias Kaehlcke To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Zhou , David Airlie , Rex Zhu Subject: [PATCH] drm/amd/powerplay: Fix enum mismatch Date: Wed, 7 Feb 2018 10:58:43 -0800 Message-Id: <20180207185843.75983-1-mka@chromium.org> X-Mailer: git-send-email 2.16.0.rc1.238.g530d649a79-goog X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Craig Bergstrom , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Justin TerAvest , Matthias Kaehlcke , amd-gfx@lists.freedesktop.org, Guenter Roeck MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP In several locations the driver uses AMD_CG_STATE_UNGATE (type enum amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum amd_powergating_stat) and vice versa. Both constants have the same value, so this doesn't cause any problems, but we still want to pass the correct type. Fixing the mismatch resolves multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7: error: implicit conversion from enumeration type 'enum amd_powergating_state' to different enumeration type 'enum amd_clockgating_state' [-Werror,-Wenum-conversion] AMD_PG_STATE_UNGATE); Signed-off-by: Matthias Kaehlcke Reviewed-by: Guenter Roeck --- drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 8 ++++---- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index 44de0874629f..416abebb8b86 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -166,10 +166,10 @@ void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) cz_dpm_powerup_uvd(hwmgr); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_UNGATE); + AMD_CG_STATE_UNGATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_PG_STATE_UNGATE); cz_dpm_update_uvd_dpm(hwmgr, false); } @@ -197,11 +197,11 @@ void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) cgs_set_clockgating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); + AMD_CG_STATE_UNGATE); cgs_set_powergating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, - AMD_CG_STATE_UNGATE); + AMD_PG_STATE_UNGATE); cz_dpm_update_vce_dpm(hwmgr); cz_enable_disable_vce_dpm(hwmgr, true); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index 69a0678ace98..402aa9cb1f78 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -162,7 +162,7 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_PG_STATE_UNGATE); smu7_update_uvd_dpm(hwmgr, false); }