From patchwork Thu Feb 15 01:42:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 10220249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 72D62601D7 for ; Thu, 15 Feb 2018 01:42:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 566D324B48 for ; Thu, 15 Feb 2018 01:42:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4AD1E2854F; Thu, 15 Feb 2018 01:42:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AA07A24B48 for ; Thu, 15 Feb 2018 01:42:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 392FD89A57; Thu, 15 Feb 2018 01:42:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9812289A16; Thu, 15 Feb 2018 01:42:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Feb 2018 17:42:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,515,1511856000"; d="scan'208";a="201226864" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.88]) by orsmga005.jf.intel.com with ESMTP; 14 Feb 2018 17:42:29 -0800 From: Rodrigo Vivi To: dri-devel@lists.freedesktop.org Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs. Date: Wed, 14 Feb 2018 17:42:24 -0800 Message-Id: <20180215014224.13407-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.6 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mesa-dev@lists.freedesktop.org, James Ausmus , Lucas De Marchi , Paulo Zanoni , Rodrigo Vivi MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Let's sync CNL ids with Spec and kernel. Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.")' and commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' Cc: James Ausmus Cc: Lucas De Marchi Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Rafael Antognolli . --- intel/intel_chipset.h | 52 +++++++++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3818e71e..01d250e8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -241,16 +241,20 @@ #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 -#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 -#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A -#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 -#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A -#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 -#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 -#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 -#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 -#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 -#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 +#define PCI_CHIP_CANNONLAKE_0 0x5A51 +#define PCI_CHIP_CANNONLAKE_1 0x5A59 +#define PCI_CHIP_CANNONLAKE_2 0x5A41 +#define PCI_CHIP_CANNONLAKE_3 0x5A49 +#define PCI_CHIP_CANNONLAKE_4 0x5A52 +#define PCI_CHIP_CANNONLAKE_5 0x5A5A +#define PCI_CHIP_CANNONLAKE_6 0x5A42 +#define PCI_CHIP_CANNONLAKE_7 0x5A4A +#define PCI_CHIP_CANNONLAKE_8 0x5A50 +#define PCI_CHIP_CANNONLAKE_9 0x5A40 +#define PCI_CHIP_CANNONLAKE_10 0x5A54 +#define PCI_CHIP_CANNONLAKE_11 0x5A5C +#define PCI_CHIP_CANNONLAKE_12 0x5A44 +#define PCI_CHIP_CANNONLAKE_13 0x5A4C #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -515,20 +519,20 @@ IS_GEMINILAKE(devid) || \ IS_COFFEELAKE(devid)) -#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) - -#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) - -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ - IS_CNL_Y(devid)) +#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_3 || \ + (devid) == PCI_CHIP_CANNONLAKE_4 || \ + (devid) == PCI_CHIP_CANNONLAKE_5 || \ + (devid) == PCI_CHIP_CANNONLAKE_6 || \ + (devid) == PCI_CHIP_CANNONLAKE_7 || \ + (devid) == PCI_CHIP_CANNONLAKE_8 || \ + (devid) == PCI_CHIP_CANNONLAKE_9 || \ + (devid) == PCI_CHIP_CANNONLAKE_10 || \ + (devid) == PCI_CHIP_CANNONLAKE_11 || \ + (devid) == PCI_CHIP_CANNONLAKE_12 || \ + (devid) == PCI_CHIP_CANNONLAKE_13) #define IS_GEN10(devid) (IS_CANNONLAKE(devid))