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[210.140.84.216]) by smtp.gmail.com with ESMTPSA id h191-v6sm10543832pgc.11.2018.05.18.02.29.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 May 2018 02:29:31 -0700 (PDT) From: Qiang Yu To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH RFC 03/24] arm64/dts: add switch-delay for meson mali Date: Fri, 18 May 2018 17:27:54 +0800 Message-Id: <20180518092815.25280-4-yuq825@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180518092815.25280-1-yuq825@gmail.com> References: <20180518092815.25280-1-yuq825@gmail.com> X-Mailman-Approved-At: Mon, 21 May 2018 08:18:09 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Shields , Marek Vasut , Connor Abbott , Neil Armstrong , Andrei Paulau <7134956@gmail.com>, Vasily Khoruzhick , Qiang Yu , Erico Nunes MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Meson mali GPU operate in high clock frequency, need this value be high to work in a stable state. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi index eb327664a4d8..8bed15267c9c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi @@ -23,6 +23,7 @@ "pp2", "ppmmu2"; clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; clock-names = "bus", "core"; + switch-delay = <0xffff>; /* * Mali clocking is provided by two identical clock paths