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[84.106.84.65]) by smtp.gmail.com with ESMTPSA id m65-v6sm1104243wmd.1.2018.06.19.13.18.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Jun 2018 13:18:34 -0700 (PDT) From: Hans de Goede X-Google-Original-From: Hans de Goede To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Daniel Vetter Subject: [PATCH 4/4] drm/i915/intel_dsi: Read back pclk set by GOP and use that as pclk Date: Tue, 19 Jun 2018 22:18:27 +0200 Message-Id: <20180619201827.4257-5-hdegoede@redhat.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180619201827.4257-1-hdegoede@redhat.com> References: <20180619201827.4257-1-hdegoede@redhat.com> X-Mailman-Approved-At: Wed, 20 Jun 2018 07:29:34 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hans de Goede , intel-gfx , dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP On BYT and CHT the GOP sometimes initializes the pclk at a (slightly) different frequency then the pclk which we've calculated. This commit makes the DSI code read-back the pclk set by the GOP and if that is within a reasonable margin of the calculated pclk, uses that instead. This fixes the first modeset being a full modeset instead of a fast modeset on systems where the GOP pclk is different. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index 4d6ffa7b3e7b..d4cc6099012c 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -517,6 +517,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) u32 mul; u16 burst_mode_ratio; enum port port; + enum pipe pipe; DRM_DEBUG_KMS("\n"); @@ -583,6 +584,19 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) } else burst_mode_ratio = 100; + /* + * On BYT / CRC the GOP sometimes picks a slightly different pclk, + * read back the GOP configured pclk and prefer it over ours. + */ + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + intel_dsi_get_hw_state(&intel_dsi->base, &pipe)) { + u32 gop = intel_dsi_get_pclk(&intel_dsi->base, bpp, NULL); + + DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", pclk, gop); + if (gop >= (pclk * 9 / 10) && gop <= (pclk * 11 / 10)) + pclk = gop; + } + intel_dsi->burst_mode_ratio = burst_mode_ratio; intel_dsi->pclk = pclk;