From patchwork Tue Jun 19 23:45:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10475645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 88F8D60353 for ; Tue, 19 Jun 2018 23:46:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7919928C77 for ; Tue, 19 Jun 2018 23:46:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DC8F28C85; Tue, 19 Jun 2018 23:46:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 24A8428C77 for ; Tue, 19 Jun 2018 23:46:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 400126E64B; Tue, 19 Jun 2018 23:46:29 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 364316E64B for ; Tue, 19 Jun 2018 23:46:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Jun 2018 16:46:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,245,1526367600"; d="scan'208";a="58651700" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by FMSMGA003.fm.intel.com with ESMTP; 19 Jun 2018 16:46:27 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: dri-devel@lists.freedesktop.org Subject: [PATCH libdrm 2/2] intel: Introducing Amber Lake platform Date: Tue, 19 Jun 2018 16:45:21 -0700 Message-Id: <20180619234521.20713-2-jose.souza@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180619234521.20713-1-jose.souza@intel.com> References: <20180619234521.20713-1-jose.souza@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= , Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. This is a copy of merged i915's commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza Reviewed-by: Rodrigo Vivi --- intel/intel_chipset.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 44e65f9e..583d6447 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -201,7 +201,6 @@ #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E -#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 @@ -213,6 +212,9 @@ #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 + #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 @@ -468,12 +470,13 @@ #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \