| Message ID | 20180809054119.13589-1-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [libdrm] drm/i915/cfl: Add a new CFL PCI ID. | expand |
On Wed, 2018-08-08 at 22:41 -0700, Rodrigo Vivi wrote: > One more CFL ID added to spec. > > Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: > Add a new CFL PCI ID.") > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > intel/intel_chipset.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 583d6447..4a34b7be 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -230,7 +230,8 @@ > #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 > #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 > #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 > -#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A > +#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E98 > +#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E9A > #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B > #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 > #define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 > @@ -509,7 +510,8 @@ > (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_1 || \ > (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_2 || \ > (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_3 || \ > - (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_4) > + (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_4 || \ > + (devid) == > PCI_CHIP_COFFEELAKE_S_GT2_5) > > #define IS_CFL_H(devid) ((devid) == > PCI_CHIP_COFFEELAKE_H_GT2_1 || \ > (devid) == > PCI_CHIP_COFFEELAKE_H_GT2_2)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 583d6447..4a34b7be 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -230,7 +230,8 @@ #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 -#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A +#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E98 +#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E9A #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 #define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 @@ -509,7 +510,8 @@ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4) + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_5) #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
One more CFL ID added to spec. Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: Add a new CFL PCI ID.") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- intel/intel_chipset.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)