From patchwork Wed Sep 12 18:32:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 10598137 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02BA714E5 for ; Wed, 12 Sep 2018 18:32:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EADBF2AA47 for ; Wed, 12 Sep 2018 18:32:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DE2E92AA60; Wed, 12 Sep 2018 18:32:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9B23C2AA47 for ; Wed, 12 Sep 2018 18:32:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C45C6E5BF; Wed, 12 Sep 2018 18:32:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kmu-office.ch (mail.kmu-office.ch [IPv6:2a02:418:6a02::a2]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7CB296E5BF for ; Wed, 12 Sep 2018 18:32:41 +0000 (UTC) Received: from trochilidae.toradex.int (75-146-58-181-Washington.hfc.comcastbusiness.net [75.146.58.181]) by mail.kmu-office.ch (Postfix) with ESMTPSA id C59015C1D14; Wed, 12 Sep 2018 20:32:35 +0200 (CEST) From: Stefan Agner To: linus.walleij@linaro.org, Laurent.pinchart@ideasonboard.com, airlied@linux.ie, robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de Subject: [PATCH v2 2/8] drm/pl111: simplify bridge timing support Date: Wed, 12 Sep 2018 11:32:16 -0700 Message-Id: <20180912183222.25414-3-stefan@agner.ch> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180912183222.25414-1-stefan@agner.ch> References: <20180912183222.25414-1-stefan@agner.ch> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, max.krummenacher@toradex.com, marcel.ziswiler@toradex.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, sean@poorly.run, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Simplify bridge timing support by only supporting pixel clock polarity. This aligns pixel clock polarity handling for bridges with displays. Signed-off-by: Stefan Agner --- drivers/gpu/drm/pl111/pl111_display.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index 754f6b25f265..31eb62e4476f 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -196,23 +196,13 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, const struct drm_bridge_timings *btimings = bridge->timings; /* - * Here is when things get really fun. Sometimes the bridge - * timings are such that the signal out from PL11x is not - * stable before the receiving bridge (such as a dumb VGA DAC - * or similar) samples it. If that happens, we compensate by - * the only method we have: output the data on the opposite - * edge of the clock so it is for sure stable when it gets - * sampled. - * - * The PL111 manual does not contain proper timining diagrams - * or data for these details, but we know from experiments - * that the setup time is more than 3000 picoseconds (3 ns). - * If we have a bridge that requires the signal to be stable - * earlier than 3000 ps before the clock pulse, we have to - * output the data on the opposite edge to avoid flicker. + * Use LCD Timing 2 Register Invert Pixel Clock (IPC) bit + * to make sure to drive data on falling edge if requested + * by bridge. */ - if (btimings && btimings->setup_time_ps >= 3000) - tim2 ^= TIM2_IPC; + if (btimings && btimings->input_bus_flags & + DRM_BUS_FLAG_PIXDATA_NEGEDGE) + tim2 |= TIM2_IPC; } tim2 |= cpl << 16;